Philips Semiconductors
Octal D-type flip-flop with data enable;
positive-edge trigger
Product specification
74AHC377; 74AHCT377
AC CHARACTERISTICS
Type 74AHC377
GND = 0 V; tr = tf ≤ 3.0 ns.
SYMBOL
PARAMETER
TEST CONDITIONS
WAVEFORMS CL
Tamb (°C)
25
−40 to +85 −40 to +125 UNIT
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VCC = 3.0 to 3.6 V; typical values at VCC = 3.3 V
tPHL/tPLH
fmax
propagation delay
CP to Qn
maximum clock pulse
frequency
see Figs 6 and 8 15 pF −
see Figs 6 and 8
80
tPHL/tPLH
tW
propagation delay
CP to Qn
clock pulse width
HIGH or LOW
see Figs 6 and 8 50 pF −
see Figs 6 and 8
5.0
tsu
set-up time Dn to CP see Figs 7 and 8
5.0
set-up time E to CP
5.0
th
hold time Dn to CP
1.5
hold time E to CP
1.5
fmax
maximum clock pulse see Figs 6 and 8
50
frequency
5.6 12.8 1.0
125 −
70
8.0 16.0 1.0
−−
5.0
−−
5.0
−−
5.0
−−
1.5
−−
1.5
75 −
45
15.0 1.0
−
70
18.0 1.0
−
5.0
−
5.0
−
5.0
−
1.5
−
1.5
−
45
16.0 ns
−
MHz
20.0 ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
MHz
VCC = 4.5 to 5.5 V; typical values at VCC = 5.0 V
tPHL/tPLH propagation delay
CP to Qn
see Figs 6 and 8 15 pF − 3.9 9.0
fmax
maximum clock pulse see Figs 6 and 8
frequency
125 175 −
1.0 10.5 1.0 11.5 ns
110 −
110 −
MHz
tPHL/tPLH
tW
propagation delay
CP to Qn
clock pulse width
HIGH or LOW
see Figs 6 and 8 50 pF − 5.6 10.5 1.0 12.0 1.0 13.5 ns
see Figs 6 and 8
5.0 − −
5.0 −
5.0 −
ns
tsu
set-up time Dn to CP see Figs 7 and 8
tsu
set-up time E to CP
th
hold time Dn to CP
th
hold time E to CP
fmax
maximum clock pulse see Figs 6 and 8
frequency
4.5 − −
4.5 − −
2.0 − −
2.0 − −
85 120 −
4.5 −
4.5 −
2.0 −
2.0 −
75 −
4.5 −
4.5 −
2.0 −
2.0 −
75 −
ns
ns
ns
ns
MHz
2000 Aug 15
9