Philips Semiconductors
Octal D-type transparent latch; 3-state
Product specification
74AHC373; 74AHCT373
handbook, full pagewidth
VI
OE input
VM(1)
GND
output
LOW-to-OFF
OFF-to-LOW
VCC
VOL
output
HIGH-to-OFF
OFF-to-HIGH
VOH
GND
tPLZ
tPZL
tPHZ
VOL + 0.3 V
VOH − 0.3 V
VM
tPZH
VM
outputs
enabled
outputs
disabled
outputs
enabled
MNA450
FAMILY
VI INPUT
REQUIREMENTS
VM
INPUT
VM
OUTPUT
AHC
AHCT
GND to VCC
GND to 3.0 V
50% VCC 50% VCC
1.5 V
50% VCC
Fig.9 The 3-state enable and disable times.
handbook, full pagewidth
Dn input
LE input
VM
th
tsu
VM
th
tsu
MNA193
FAMILY
AHC
AHCT
VI INPUT
REQUIREMENTS
GND to VCC
GND to 3.0 V
VM
INPUT
50% VCC
1.5 V
VM
OUTPUT
50% VCC
50% VCC
The shaded areas indicate when the input is permitted to change for predicable output performance.
Fig.10 The data set-up and hold times for Dn input to LE input.
1999 Nov 23
13