
Connection Diagram
Logic Symbols
IEEE/IEC
Pin Descriptions
Pin Names
D0–D7
MR
CP
Q0–Q7
Description
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
Mode Select-Function Table
Operating Mode
Reset (Clear)
Load ‘1'
Load ‘0'
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
LOW-to-HIGH Transition
Inputs
Outputs
MR CP Dn
Qn
LXX
L
H
H
H
H
L
L
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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