56F802(2005) View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
56F802 Datasheet PDF : 40 Pages
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3.5.2 Phase Locked Loop Timing
Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 3-9 PLL Timing
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency for the PLL1
fosc
4
8
10
MHz
PLL output frequency2
fout/2
40
—
803
MHz
PLL stabilization time4 0o to +85oC
tplls
—
10
—
ms
PLL stabilization time4 -40o to 0oC
tplls
—
100
200
ms
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.
2. ZCLK may not exceed 80MHz. For additional information on ZCLK and fout/2, please refer to the OCCS chapter in the
User Manual. ZCLK = fop
3. Will not exceed 60MHz for the DSP56F802TA60 device.
4. This is the minimum time required after the PLL setup is changed to ensure reliable operation.
3.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 3-10 Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 3
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic
Symbol
Min
Max
Unit
RESET Assertion to Address, Data and Control Signals High
tRAZ
—
Impedance
21
ns
Minimum RESET Assertion Duration2
OMR Bit 6 = 0
OMR Bit 6 = 1
tRA
275,000T
—
ns
128T
—
ns
RESET De-assertion to First External Address Output
tRDA
33T
34T
ns
Edge-sensitive Interrupt Request Width
tIRW
1.5T
—
ns
1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
• After power-on reset
• When recovering from Stop state
3. Parameters listed are guaranteed by design.
56F802 Technical Data, Rev. 7
Freescale Semiconductor
25
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