PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
FUNCTIONAL BLOCK DIAGRAM
32 Meg x 4
CKE
CK#
CK
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
MODE REGISTERS
12
REFRESH 12
COUNTER
ROW-
12
ADDRESS
MUX
12
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
4096
BANK0
MEMORY
ARRAY
(4,096 x 1,024 x 8)
SENSE AMPLIFIERS
8192
4
8
READ
LATCH 4
MUX
CK
DATA
DLL
4
DQS
GENERATOR
DRVRS
1
A0-A11,
BA0, BA1
14
ADDRESS
REGISTER
2
BANK
CONTROL
LOGIC
2
COLUMN-
ADDRESS
10
11
COUNTER/
LATCH
1
I/O GATING
DM MASK LOGIC
8
1024
(x8)
COLUMN
DECODER
COL0
INPUT
REGISTERS
DQS
1
MASK
WRITE
1
8
FIFO
2
&
DRIVERS
4
8
ck
ck
4
out
in DATA
1
1
1
RCVRS
4
4
4
CK
1
COL0
DQ0 -
DQ3, DM
DQS
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
4
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©2001, Micron Technology, Inc.