AD5724 View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

AD5724

Complete, Quad, 12-/14-/16-Bit, Serial Input, Unipolar/Bipolar Voltage Output DACs

Analog Devices 

AD5724/AD5734/AD5754

Data Sheet

POWER CONTROL REGISTER

The power control register is addressed by setting the three REG bits to 010. This register allows the user to control and determine the

power and thermal status of the AD5724/AD5734/AD5754. The power control register options are shown in Table 26 and Table 27.

Table 26. Programming the Power Control Register

MSB

DB15 to

R/W Zero REG2 REG1 REG0 A2 A1 A0 DB11

0

0

0

1

0

000X

LSB

DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

OCD OCC OCB OCA 0

TSD 0

PUD PUC PUB PUA

Table 27. Power Control Register Functions

Option Description

PUA

DAC A power-up. When set, this bit places DAC A in normal operating mode. When cleared, this bit places DAC A in power-down

mode (default). After setting this bit to power DAC A, a power up time of 10 µs is required. During this power-up time, the DAC

register must not be loaded to the DAC output (see the Load DAC/LDAC section). If the clamp enable bit of the control register is

cleared, DAC A powers down automatically upon detection of an overcurrent, and PUA is cleared to reflect this.

PUB

DAC B power-up. When set, this bit places DAC B in normal operating mode. When cleared, this bit places DAC B in power-down

mode (default). After setting this bit to power DAC B, a power up time of 10 µs is required. During this power-up time, the DAC

register must not be loaded to the DAC output (see the Load DAC/LDAC section). If the clamp enable bit of the control register is

cleared, DAC B powers down automatically upon detection of an overcurrent, and PUB is cleared to reflect this.

PUC

DAC C power-up. When set, this bit places DAC C in normal operating mode. When cleared, this bit places DAC C in power-down

mode (default). After setting this bit to power DAC C, a power up time of 10 µs is required. During this power-up time, the DAC

register must not be loaded to the DAC output (see the Load DAC/LDAC section). If the clamp enable bit of the control register is

cleared, DAC C powers down automatically upon detection of an overcurrent, and PUC is cleared to reflect this.

PUD

DAC D power-up. When set, this bit places DAC D in normal operating mode. When cleared, this bit places DAC D in power-down

mode (default). After setting this bit to power DAC D, a power up time of 10 µs is required. During this power-up time, the DAC

register must not be loaded to the DAC output (see the Load DAC/LDAC section). If the clamp enable bit of the control register is

cleared, DAC D powers down automatically upon detection of an overcurrent, and PUD is cleared to reflect this.

TSD

Thermal shutdown alert. Read-only bit. In the event of an overtemperature situation, the four DACs are powered down and this

bit is set.

OCA

DAC A overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC A, this bit is set.

OCB

DAC B overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC B, this bit is set.

OCC

DAC C overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC C, this bit is set.

OCD

DAC D overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC D, this bit is set.

Rev. F | Page 26 of 31

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