AD8318(2006) View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
AD8318 Datasheet PDF : 24 Pages
| |||
CHARACTERIZATION SETUP AND METHODS
The general hardware configuration used for the AD8318
characterization is shown in Figure 46. The primary setup used for
characterization is measurement mode. The characterization board
is similar to the customer evaluation board with the exception that
the RF input has a Rosenberger SMA connector and R10 has
changed to a 1 kΩ resistor to remove cable capacitance from the
bench characterization setup. Slope and intercept are calculated in
this data sheet and in the production environment using linear
regression from −50 dBm to −10 dBm. The slope and intercept
generate an ideal line. Log conformance error is the difference from
the ideal line and the measured output voltage for a given tempera-
ture in dB. For additional information on the error calculation, refer
to the Device Calibration and Error Calculation section.
The hardware configuration for pulse response measurement
replaces the 0 Ω series resistor at the VOUT pin with a 40 Ω resistor;
the CLPF pin remains open. Pulse response time is measured using a
Tektronix TDS51504 Digital Phosphor Oscilloscope. Both channels
on the scope are configured for 50 Ω termination. The 10 Ω internal
series resistance at VOUT, combined with the 40 Ω resistor,
attenuates the output voltage level by two. RF input frequency is set
to 100 MHz with −10 dBm at the input of the device. The RF burst is
generated using a Rohde & Schwarz SMT06 with the pulse option
with a period of 1.5 μs, a width of 0.1 μs, and a pulse delay of 0.04 μs.
The output response is triggered using the video output from the
SMT06. Refer to Figure 46 for an overview of the test setup.
AD8318
R AND S SMT06
VIDEO RF OUT
OUT –7dBm
3dB
SPLITTER 1nF
52.3Ω
1nF
5V
VPOS
INHI
VOUT
AD8318
INLO
VSET
GND
TEKTRONIX
TDS51504
CH1* CH3* TRIGGER
40Ω
*50Ω
TERMINATION
Figure 46. Pulse Response Measurement Test Setup
To measure noise spectral density, the 0 Ω resistor in series with
the VOUT pin is replaced with a 1 μF dc blocking capacitor.
The capacitor is used because the Rohde & Schwarz FSEA
spectrum analyzer cannot handle dc voltages at its RF input.
The CLPF pin is left open for data collected for Figure 18. For
Figure 19, a 1 μF capacitor is placed between CLPF and ground.
The large capacitor filters the noise from the detector stages of
the log amp. Noise spectral density measurements are taken
using the FSEA and the SMT06 signal generator. The signal
generator frequency is set to 2.2 GHz. The spectrum analyzer
has a span of 10 Hz, resolution bandwidth of 50 Hz, video
bandwidth of 50 Hz, and averages the signal 100 times. Data is
adjusted to account for the dc blocking capacitor impedance on
the output at lower frequencies.
Rev. A | Page 21 of 24
Share Link: 