53C810 View Datasheet(PDF) - Unspecified
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MFG CO.
53C810 Datasheet PDF : 140 Pages
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PREUMINARY
Chapter Three
PCI Functional Description
Chapter Three
PCI Functional
Description
PCI Addressing
There are three types of PCI-defmed address
space:
Configuration space
Memory space
I/O space
Configuration space is a contiguous 256 8-bit set
of addresses dedicated to each "slot" or "stub" on
the bus. A decode of C_BE/(3-0) determines if
this PCI cycle is intended to access configuration
register space. The IDSEL bus signal is a "chip
select" that allows access to the configuration
register space only. A configuration read/write
cycle without IDSEL will be ignored. The eight
lower order addresses are used to select a specific
8-bit register. The host uses this configuration
space to initialize the 53C810.
The lower 128 bytes of the 53C810's 256-byte
configuration space holds system parameters
while the upper 128 bytes maps into the 53C810
operating registers. For all PCI cycles except
configuration cycles, the 53C810 registers are
located on the 256-byte block boundary defined
by the system assigned (through the configured
register) base address. The 53 C81 0 operating
registers will be available in both the upper and
lower 128-byte portions of the 256-byte space
selected.
Table 3-1. PCI Bus Commands and Encoding Types
CBE/(3-0)
Command Type
Supported
as Master
Supported
as Slave
0000
Interrupt Acknowledge
No
No
0001
Special Cycle
No
No
0010
I/O Read Cycle
Yes
Yes
0011
I/O Write Cycle
Yes
Yes
0100
Reserved
nla
0101
Reserved
nJa
0110
Memory Read
Yes
Yes
0111
Memory Write
Yes
Yes
1000
Reserved
nla
1001
Reserved
nla
1010
Configuration Read
No
Yes
1011
Configuration Write
No
Yes
1100
Memory Read Multiple
No
Yes*
1101
Reserved
nla
1110
Memory Read Line
Yes**
Yes*
1111
Memory Write and Invalidate
No
Yes*
* These cycles will be interpreted as standard memory reads or writes ** This operation is se/e.ctable by bit 3 in the DMODE register
NCR 53C81 0 Data Manual
3-1
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