53C810 View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
53C810 Datasheet PDF : 140 Pages
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PREIlMINARY
Chapter Two
Functional Description
Loopback Mode
Parity Options
The 53C810 loopback mode allows testing of
both initiator and target functions and, in effect,
lets the chip communicate with itself. When the
Loopback Enable bit is set in the STEST1 regis-
ter, the 53C810 allows control of all SCSI signals,
whether the 53C810 is operating in initiator or
target mode.
The 53C810 implements a flexible parity scheme
that allows control of the parity sense, alloWs parity
checking to be turned on or off, and has the ability
to deliberately send a byte with bad parity over the
SCSI bus to test parity error recovery procedures.
The following bits are involved in parity control
and observation:
1) Assert ATN/ on Parity Errors - Bit 1 in the
SCNTLO register. This bit causes the 53C810
-to automatically assert SCSI ATN/ when it
detects a parity error while operating as an
initiator.
2) Enable Parity Checking - Bit 3 in the
SCNTLO register. This bit enables the
53C810 to check for parity errors. The
53C810 checks for odd parity.
3) Assert Even SCSI Parity - Bit 2 in the
SCNTL1 register. This bit determines the
SCSI parity sense checked and generated.by
the 53C810.
4) Disable Halt on ATN/ or a Parity Error
(Target Mode Only) - Bit 5 in the SCNTL1
register. This bit causes the 53C810 to halt
operations when a parity error is detected in
target mode.
5) Enable Parity Error Interrupt - Bit 0 in the
SIENO register. This bit determines whether
the 53C810 will generate an interrupt when it
detects a SCSI parity error.
6) Parity Error - Bit 0 in the SISTO register. This
status bit is set whenever the 53 C81 0 has
detected a parity error on the SCSI bus.
7) Status of SCSI Parity Signal - Bit 0 in the
SSTATO register. This status bit represents
the live SCSI Parity Signal (SDP).
8) Latched SCSI Parity Signal - Bit 3 in the
SSTAT 1 register.
NCR 53C810 Data Manual
2-3
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