53C810 View Datasheet(PDF) - Unspecified

Part Name

Description

MFG CO.

53C810

PCI-SCSI I/O Processor

Unspecified 

Chapter Two

Functional Description

PREllMINARY

pares with 2-8 ms required for traditional intelli-

gent host adapters. Algorithms may be designed

- to tune SCSI bus performance, to adjust to new

bus device types (Le., scanners, communication

gateways, etc.), or to incorporate changes in the

SCSI-2 or SCSI-3 logical bus definitions without

sacrificing 110 performance. SCSI SCRIPTS are

independent of the type of CPU or system bus in

use.

The 53C810 can be programmed with SCSI

SCRIPTS, including advanced SCSI SCRIPTS

capabilitities. A complete set of development

tools is available for writing custom drivers with

SCSI SCRIPTS.

Executing SCRIPTS

Instructions

After power up and initialization of the 53C810,

the chip may be operated in low level (register

interface) mode, or in SCSI SCRIPTS mode.

To operate in SCSI SCRIPTS mode, the

53C810 requires only a SCRIPTS start address.

All SCRIPTS commands are fetched from local

or external memory. The 53C810 fetches and

executes its own instructions by becoming a bus

master on the host bus and fetching two or three

32-bit words into its registers. .Commands are

fetched until an unexpected event causes an

interrupt to the external processor. SCSI

SCRIPTS operation ofiloads the microprocessor

from servicing the numerous interrupts inherent

in 110 operations. Four·types of SCRIPTS

instructions are available in the 53C810: Block

Move, 110 or ReadlWrite, Transfer Control, and

Memory Move. Each instruction consists of two

or three 32-bit words. The first 32-bit word is

always loaded into the PCMD and DBC regis-

ters, the second into the DSPS register. The

third word, used only by Memory Move instruc-

tions, is loaded into the TEMP shadow register.

Block Move instructions allow indirect address-

ing, table indirect addressing, and chained block

moves, depending on bit settings in the DCMD,

DBC, and DSPS registers. 110 instructions allow

table indirect mode, relative address mode, and

options to set or clear the carry bit in the ALU.

ReadlWrite instructions include read-modify-

write cycles and moves to and from the SFBR

register. Transfer Control instructions include

jump, call, return, interrupt (including interrupt-

on-the-fly), and relative addressing mode.

Memory Move instructions allow the transfer of

single or multiple register values to or from

system memory, to free the system processor tor

other tasks and move data at higher speeds than

available fi.:om current DMA controllers. JJp to

16 MB may be transferred with one instruction.

SDMS: The Total SCSI

Solution

The 53C810 provides a total SCSI solution in

PC environments with the NCR SCSI Device

Management System (SDMS). SDMS provides

BIOS driver support for hard disk, tape, and

removable media peripherals for the DOS,

Windows™, OS/2™, and Novell operating

environments. The NCR SCSI Evaluation Kit is

available to system developers and contains

SDMS evaluation software, an evaluation SCSI

board, and full documentation for the kit compo-

nents.

TheSDMS includes a SCSI BIOS (CAMcore),

resident in the SCSI controller or processor, to

manage all SCSI functions related to the device.

SDMS also provides a series of SCSI device

drivers (CAMpliant modules) that support most

major operating systems. SDMS supports multi-

threaded I/O application programming interface

(API) for user-developed SCSI applications.

2-2

NCR 53C81 0 Data Manual

Share Link: