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EP2C50AQ324I7ES View Datasheet(PDF) - Altera Corporation

Part Name
Description
MFG CO.
EP2C50AQ324I7ES
Altera
Altera Corporation 
EP2C50AQ324I7ES Datasheet PDF : 168 Pages
First Prev 161 162 163 164 165 166 167 168
DC Characteristics and Timing Specifications
February 2007 Added document revision history.
v3.1
Added VCCA minimum and maximum limitations in
Table 5–1.
Updated Note (1) in Table 5–2.
Updated the maximum VCC rise time for Cyclone II
“A” devices in Table 5–2.
Updated RCONF information in Table 5–3.
Changed VI to Ii in Table 5–3.
Updated LVPECL clock inputs in Note (6) to
Table 5–8.
Updated Note (1) to Table 5–12.
Updated CV R E F capacitance description in
Table 5–13.
Updated “Timing Specifications” section.
Updated Table 5–45.
Added Table 5–46 with information on toggle rate
derating factors.
Corrected calculation of the period based on a
640 Mbps data rate as 1562.5 ps in Note (2) to
Table 5–50.
Updated “PLL Timing Specifications” section.
Updated VCO range of 300–500 MHz in Note (3) to
Table 5–54.
Updated chapter with extended temperature
information.
December 2005 Updated PLL Timing Specifications
v2.2
November 2005 Updated technical content throughout.
v2.1
July 2005
Updated technical content throughout.
v2.0
November 2004 Updated the “Differential I/O Standards” section.
v1.1
Updated Table 5–54.
June 2004
Added document to the Cyclone II Device Handbook.
v1.0
Altera Corporation
February 2008
5–75
Cyclone II Device Handbook, Volume 1

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