EP2C15QT208C8ES View Datasheet(PDF) - Altera Corporation

Part Name

Description

MFG CO.

EP2C15QT208C8ES

Section I. Cyclone II Device Family Data Sheet

Altera Corporation 

Duty Cycle Distortion

(T/2 – D1) / T (the low percentage boundary)

(T/2 + D2) / T (the high percentage boundary)

DCD Measurement Techniques

DCD is measured at an FPGA output pin driven by registers inside the

corresponding I/O element (IOE) block. When the output is a single data

rate signal (non-DDIO), only one edge of the register input clock (positive

or negative) triggers output transitions (Figure 5–9). Therefore, any DCD

present on the input clock signal, or caused by the clock input buffer, or

different input I/O standard, does not transfer to the output signal.

Figure 5–9. DCD Measurement Technique for Non-DDIO (Single-Data Rate) Outputs

IOE

DFF

DQ

output

clk

However, when the output is a double data rate input/output (DDIO)

signal, both edges of the input clock signal (positive and negative) trigger

output transitions (Figure 5–10). Therefore, any distortion on the input

clock and the input clock buffer affect the output DCD.

5–68

Cyclone II Device Handbook, Volume 1

Altera Corporation

February 2008

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