AN221D04-DEVLP View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
AN221D04-DEVLP Datasheet PDF : 21 Pages
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AN221E04 Datasheet – Dynamically Reconfigurable FPAA With Enhanced I/O
PINOUT
Pin
Numb
er
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin
Name
I4PA
I4NA
O1P
O1N
AVSS
AVDD
O2P
O2N
I1P
I1N
I2P
I2N
SHIELD
AVDD2
VREFMC
VREFPC
VMRC
BVDD
BVSS
CFGFLGb
Pin
Type
Analog IN+
Analog IN-
Analog OUT+
Analog OUT-
Analog Vss
Analog Vdd
Analog OUT
Analog OUT
Analog IN+
Analog IN-
Analog IN+
Analog IN-
Analog Vdd
Analog Vdd
Vref
Vref
Vref
Analog Vdd
Analog Vss
Digital IN
Digital OUT
21
CS2b
Digital IN
22
CS1b
23
DCLK
24
SVSS
25
MODE
Digital IN
(during config)
Digital IN
(after config)_
Digital IN
Digital Vss
Digital IN
26
ACLK / SPIP Digital IN
Digital OUT
27
OUTCLK /
Digital OUT
SPIMEM
Digital OUT
28
DVDD
Digital Vdd
29
DVSS
Digital Vss
30
DIN
Digital IN
31
LCCb
Digital OUT
32
ERRb
Digital IN
(monitored OUT)
Digital OUT
33
ACTIVATE
Digital IN
34
DOUTCLK / Digital OUT
TEST
Digital IN
35
PORb
Digital IN
36
EXECUTE
Digital IN
37
I3P
38
I3N
39
I4PD
Analog IN+
Analog IN-
Analog IN+
40
I4ND
41
I4PC
42
I4NC
43
I4PB
44
I4NB
Analog IN-
Analog IN+
Analog IN-
Analog IN+
Analog IN-
Comments
Low noise Vdd bias for capacitor array n-wells
Analog power
Attach filter capacitor for VREF-
Attach filter capacitor for VREF+
Attach filter capacitor for VMR (Voltage Main Reference)
Analog power for bandgap Vref Generators
Analog ground for bandgap Vref Generators
In multi-device systems...
0, Ignore incoming data (unless currently addressed)
1, Pay attention to incoming data (watching for address)
0, Device is being configured
Z, Device is not being configured (if internal pullup is selected)
0, Chip is selected
1, Chip is not selected
0, Allow configuration to proceed
1, Hold off configuration
Passes read-back data through to LCC_B pin
Digital ground - substrate tie
0, Synchronous serial interface
1, SPI EPROM Interface
MODE = 0, analog clock < 40 MHz
MODE = 1, SPI EPROM or serial EPROM clock
During power-up, sources SPI EPROM initialization command string
After power-up, sources any of the four internal analog clocks
Serial configuration data input
1, Local configuration is needed. Once configuration is completed, it is a registered version of
CS1b or if the device is addressed for read, it serves as serial data out port
0, Initiate reset
1, No action
0, Error condition
Z, No error condition (external pullup required)
0, Hold off completion of configuration
Rising Edge, Allow completion of configuration
O.D. Output 0, device has not yet completed primary configuration
Z, Device has completed primary configuration (if internal pullup is selected)
A buffered version of DCLK.
(Factory reserved test input. Float if unused)
0, Chip held in reset state
Rising edge, re-initiates power on reset sequence
To initiate a POR reset cycle, the minimum pulse width required on the PORb pin is 25ns.
0, No action
1, Transfer shadow RAM into configuration RAM
Analog multiplexer input signals.
The multiplexer can accept 4 differential inputs or 8 single ended inputs
DS030100-U006a - 16 -
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