SC28L194A1BE View Datasheet(PDF) - Philips Electronics

Part Name

Description

MFG CO.

SC28L194A1BE

Quad UART for 3.3V and 5V supply voltage

Philips Electronics 

Philips Semiconductors

Quad UART for 3.3V and 5V supply voltage

Preliminary specification

SC28L194

Table 4. MR1 - Mode Register 1

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Bit 7

Bit 6

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ RxRTS Control

ISR Read Mode

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 0 - off

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 1 - on

0 - ISR unmasked

1 - ISR masked

Bit 5

Error Mode

0 = Character

1 = Block

Bit 4:3

Parity Mode

00 - With Parity

01 - Force parity

10 - No parity

11 - Special Mode

Bit 2

Parity Type

0 = Even

1 = Odd

Bit 1:0

Bits per Character

00 - 5

01 - 6

10 - 7

11 - 8

MR1[7]: Receiver Request to Send Control

on a character by character basis; the status applies only to the

This bit controls the deactivation of the RTSN output (I/O2) by the

character at. the bottom of the FIFO. In the block mode, the status

receiver. This output is asserted and negated by commands applied

provided in the SR for these bits is the accumulation (logical OR) of

via the command register. MR1[7] = 1 causes RTSN to be

the status for all characters coming to the top of the FIFO, since the

automatically negated upon receipt of a valid start bit if the receiver

last reset error command was issued.

FIFO is 3/4 full or greater. RTSN is reasserted when an the FIFO fill

level falls below 3/4 full. This constitutes a change from previous

members of Philips (Signets)’ UART families where the RTSN

function triggered on FIFO full. This behavior caused problems with

PC UARTs that could not stop transmission at the proper time. The

RTSN feature can be used to prevent overrun in the receiver, by

MR1[4:3]: Parity Mode Select

If ‘with parity’ or ’force parity’ is selected, a parity bit is added to the

transmitted character and the receiver performs a parity check on

incoming data. MR1[4:3] = 11 selects the channel to operate in the

special Wake-up mode.

using the RTSN output signal, to control the CTSN input of the

MR1[2]: Parity Type Select

transmitting device.

This bit sets the parity type (odd or even) if the ’with parity’ mode is

MR1[6]: Interrupt Status Masking

This bit controls the readout mode of the Interrupt Status Register,

ISR. If set, the ISR reads the current status masked by the IMR, i.e.

only interrupt sources enabled in the IMR can ever show a ‘1’ in the

ISR. If cleared, the ISR shows the current status of the interrupt

programmed by MR1[4:3], and the polarity of the forced parity bit if

the ’force parity’ mode is programmed. It has no effect if the ’no

parity’ mode is programmed. In the special ’Wake-up’ mode, it

selects the polarity of the A/D bit. The parity bit is used to an

address or data byte in the ’Wake-up’ mode.

source without regard to the Interrupt Mask setting.

MR1[1:0]: Bits per Character Select

MR1[5]: Error Mode Select

This bit selects the operating mode of the three FIFOed status bits

(FE, PE, received break). In the character mode, status is provided

This field selects the number of data bits per character to be

transmitted and received. This number does not include the start,

parity, or stop bits.

1998 Sep 21

18

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