RM7000A™ Microprocessor with On-Chip Secondary Cache Datasheet
Released
List of Figures
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Block Diagram ..........................................................................................................10
CP0 Registers ...........................................................................................................12
Instruction Issue Paradigm .......................................................................................13
Pipeline 1 ...................................................................................................................4
CP0 Registers ...........................................................................................................18
Kernel Mode Virtual Addressing (32-bit mode) .........................................................19
Tertiary Cache Hit and Miss .....................................................................................25
Typical Embedded System Block Diagram ...............................................................28
Processor Block Read ..............................................................................................30
Processor Block Write ..............................................................................................31
Multiple Outstanding Reads ......................................................................................31
Clock Timing .............................................................................................................49
Input Timing ..............................................................................................................49
Output Timing ...........................................................................................................49
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Document ID: PMC-2002175, Issue 1