MT48LC16M16A2FB-7E(2002) View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
MT48LC16M16A2FB-7E Datasheet PDF : 62 Pages
| |||
READ – DQM OPERATION 1
T0
T1
T2
T3
T4
T5
CLK
tCK
tCKS tCKH
tCL
tCH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
DQM/
DQML, DQMU
tAS tAH
tCMS tCMH
A0-A9, A11, A12
A10
ROW
tAS tAH
ROW
tAS tAH
COLUMN m 2
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BA0, BA1
BANK
BANK
DQ
tRCD
tAC
tLZ
CAS Latency
tOH
DOUT m
tHZ
tAC
tLZ
256Mb: x4, x8, x16
SDRAM
T6
T7
T8
NOP
NOP
NOP
tAC
tOH
DOUT m + 2
tOH
DOUT m + 3
tHZ
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL*
tAC (3)
tAC (2)
tAH
tAS
tCH
tCL
tCK (3)
tCK (2)
tCKH
MIN
0.8
1.5
2.5
2.5
7
7.5
0.8
-7E
MAX
5.4
5.4
-75
MIN
0.8
1.5
2.5
2.5
7.5
10
0.8
MAX
5.4
6
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL*
tCKS
tCMH
tCMS
tHZ (3)
tHZ (2)
tLZ
tOH
tRCD
MIN
1.5
0.8
1.5
1
3
15
-7E
MAX
5.4
5.4
*CAS latency indicated in parentheses.
NOTE:
1. For this example, the burst length = 4, and the CAS latency = 2.
2. x16: A9, A11, and A12 = “Don’t Care”
x8: A11 and A12 = “Don’t Care”
x4: A12 = “Don’t Care”
-75
MIN
1.5
0.8
1.5
1
3
20
MAX
5.4
6
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65 – Rev. E; Pub. 3/02
51
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
Share Link: 