1Gb: x4, x8, x16 DDR2 SDRAM
ACTIVATE
Figure 45: Multibank Activate Restriction
CK#
T0
T1
T2
T3
T4
T5
CK
Command ACT
READ
ACT
READ
ACT
READ
T6
T7
T8
ACT
READ
NOP
Address Row
Col
Row
Col
Row
Col
Row
Col
Bank address Bank a
Bank a
tRRD (MIN)
Bank b
Bank b
Bank c
Bank c
Bank d
tFAW (MIN)
Bank d
T9
T10
NOP
ACT
Row
Bank e
Don’t Care
Note: 1. DDR2-533 (-37E, x4 or x8), tCK = 3.75ns, BL = 4, AL = 3, CL = 4, tRRD (MIN) = 7.5ns, tFAW
(MIN) = 37.5ns.
PDF: 09005aef8565148a
1GbDDR2.pdf – Rev. AA 07/14 EN
91
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