MT47H64M16NF-25EM View Datasheet(PDF) - Micron Technology

Part Name

Description

MFG CO.

MT47H64M16NF-25EM

1Gb: x4, x8, x16 DDR2 SDRAM

Micron Technology 

1Gb: x4, x8, x16 DDR2 SDRAM

Electrical Specifications – IDD Parameters

Table 11: DDR2 IDD Specifications and Conditions (Die Revision M) (Continued)

Notes: 1–7 apply to the entire table

Parameter/Condition

Burst refresh current: tCK = tCK (IDD); REFRESH com-

mand at every tRFC (IDD) interval; CKE is HIGH, CS# is

HIGH between valid commands; Other control and ad-

dress bus inputs are switching; Data bus inputs are

switching

Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V;

Other control and address bus inputs are floating; Da-

ta bus inputs are floating

Operating bank interleave read

current: All bank interleaving reads, IOUT = 0mA; BL =

4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK =

tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD =

tRCD (IDD); CKE is HIGH, CS# is HIGH between valid

commands; Address bus inputs are stable during dese-

lects; Data bus inputs are switching; See IDD7 Condi-

tions (page 27) for details

Symbol

IDD5

IDD6

IDD7

Configuration

x4, x8

x16

x4, x8, x16

x4, x8

x16

-187E

165

170

7

220

270

-25E

155

160

7

210

260

-3

Units

150

mA

155

7

mA

185

mA

230

Notes:

1. IDD specifications are tested after the device is properly initialized. 0°C ≤ TC ≤ +85°C.

2. VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V, VDDL = +1.8V ±0.1V, VREF = VDDQ/2.

3. IDD parameters are specified with ODT disabled.

4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and

UDQS#. IDD values must be met with all combinations of EMR bits 10 and 11.

5. Definitions for IDD conditions:

LOW

HIGH

Stable

VIN ≤ VIL(AC)max

VIN ≥ VIH(AC)min

Inputs stable at a HIGH or LOW level

Floating Inputs at VREF = VDDQ/2

Switching Inputs changing between HIGH and LOW every other clock cycle (once per

two clocks) for address and control signals

Switching Inputs changing between HIGH and LOW every other data transfer (once

per clock) for DQ signals, not including masks or strobes

6. IDD1, IDD4R, and IDD7 require A12 in EMR to be enabled during testing.

7. The following IDD values must be derated (IDD limits increase) on IT-option and AT-option

devices when operated outside of the range 0°C ≤ TC ≤ 85°C:

When

IDD2P and IDD3P(SLOW) must be derated by 4%; IDD4R and IDD4W must be de-

TC ≤ 0°C (IT) rated by 2%; and IDD6 and IDD7 must be derated by 7%

When

85°C ≥ TC ≤

95°C (CT)

(Extended CT Temperature) IDD0, IDD1, IDD2N, IDD2Q, IDD3N, IDD3P(FAST), IDD4R,

IDD4W, and IDD5 must be derated by 2%; IDD2P must be derated by 20%;

IDD3P(SLOW) must be derated by 30%; and IDD6 must be derated by 80%

(IDD6 will increase by this amount if TC < 85°C and the 2X refresh option is

still enabled)

PDF: 09005aef8565148a

1GbDDR2.pdf – Rev. AA 07/14 EN

31

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2007 Micron Technology, Inc. All rights reserved.

Share Link: