MT47H64M16JN-187EM View Datasheet(PDF) - Micron Technology

Part Name

Description

MFG CO.

MT47H64M16JN-187EM

1Gb: x4, x8, x16 DDR2 SDRAM

Micron Technology 

1Gb: x4, x8, x16 DDR2 SDRAM

Precharge Power-Down Clock Frequency Change

Precharge Power-Down Clock Frequency Change

When the DDR2 SDRAM is in precharge power-down mode, ODT must be turned off

and CKE must be at a logic LOW level. A minimum of two differential clock cycles must

pass after CKE goes LOW before clock frequency may change. The device input clock

frequency is allowed to change only within minimum and maximum operating fre-

quencies specified for the particular speed grade. During input clock frequency change,

ODT and CKE must be held at stable LOW levels. When the input clock frequency is

changed, new stable clocks must be provided to the device before precharge power-

down may be exited, and DLL must be reset via MR after precharge power-down exit.

Depending on the new clock frequency, additional LM commands might be required to

adjust the CL, WR, AL, and so forth. Depending on the new clock frequency, an addi-

tional LM command might be required to appropriately set the WR MR9, MR10, MR11.

During the DLL relock period of 200 cycles, ODT must remain off. After the DLL lock

time, the DRAM is ready to operate with a new clock frequency.

Figure 79: Input Clock Frequency Change During Precharge Power-Down Mode

Previous clock frequency

T0

T1

T2

T3

CK#

CK

tCH tCL

tCK

2 x tCK (MIN)1

tCKE (MIN)3

CKE

Command

Valid4

NOP

New clock frequency

Ta0

Ta1

Ta2

Ta3

Ta4

tCH tCL

tCK

1 x tCK (MIN)2

tCKE (MIN)3

NOP

NOP

LM

NOP

Tb0

Valid

Address

Valid

ODT

DQS, DQS# High-Z

DQ

High-Z

DLL RESET

tXP

Valid

DM

Enter precharge

power-down mode

Frequency

change

Exit precharge

power-down mode

200 x tCK

Indicates a break in

time scale

Don’t Care

Notes:

1. A minimum of 2 × tCK is required after entering precharge power-down prior to chang-

ing clock frequencies.

2. When the new clock frequency has changed and is stable, a minimum of 1 × tCK is re-

quired prior to exiting precharge power-down.

PDF: 09005aef8565148a

1GbDDR2.pdf – Rev. AA 07/14 EN

124

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2007 Micron Technology, Inc. All rights reserved.

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