MT47H128M8NF-3LITH View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
MT47H128M8NF-3LITH Datasheet PDF : 133 Pages
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SELF REFRESH
1Gb: x4, x8, x16 DDR2 SDRAM
SELF REFRESH
The SELF REFRESH command is initiated when CKE is LOW. The differential clock
should remain stable and meet tCKE specifications at least 1 × tCK after entering self re-
fresh mode. The procedure for exiting self refresh requires a sequence of commands.
First, the differential clock must be stable and meet tCK specifications at least 1 × tCK
prior to CKE going back to HIGH. Once CKE is HIGH (tCKE [MIN] has been satisfied
with three clock registrations), the DDR2 SDRAM must have NOP or DESELECT com-
mands issued for tXSNR. A simple algorithm for meeting both refresh and DLL require-
ments is used to apply NOP or DESELECT commands for 200 clock cycles before apply-
ing any other command.
PDF: 09005aef8565148a
1GbDDR2.pdf – Rev. AA 07/14 EN
115
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