MT47H128M8SH-187EITM View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
MT47H128M8SH-187EITM Datasheet PDF : 133 Pages
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1Gb: x4, x8, x16 DDR2 SDRAM
WRITE
Figure 59: Consecutive WRITE-to-WRITE
T0
CK#
CK
T1 T1n T2 T2n T3 T3n T4 T4n T5 T5n T6
Command WRITE
NOP
WRITE
NOP
NOP
NOP
NOP
tCCD
WL = 2
WL = 2
Address
BCaonl kb,
BCaonl kn,
tDQSS (NOM)
DQS, DQS#
WL ± tDQSS
1
1
1
DQ
DbI
DnI
DM
Transitioning Data
Don’t Care
Notes:
1. Subsequent rising DQS signals must align to the clock within tDQSS.
2. DI b, etc. = data-in for column b, etc.
3. Three subsequent elements of data-in are applied in the programmed order following
DI b.
4. Three subsequent elements of data-in are applied in the programmed order following
DI n.
5. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.
6. Each WRITE command may be to any bank.
Figure 60: Nonconsecutive WRITE-to-WRITE
T0
CK#
CK
T1
T2 T2n T3 T3n T4 T4n T5 T5n T6 T6n
Command WRITE
NOP
NOP
WRITE
NOP
NOP
NOP
WL = 2
WL = 2
Address
tDQSS (NOM)
DQS, DQS#
BCaonl kb,
WL ± tDQSS
BCaonl kn,
1
1
1
DQ
DbI
DnI
DM
Transitioning Data
Don’t Care
Notes:
1. Subsequent rising DQS signals must align to the clock within tDQSS.
2. DI b (or n), etc. = data-in for column b (or column n).
3. Three subsequent elements of data-in are applied in the programmed order following
DI b.
4. Three subsequent elements of data-in are applied in the programmed order following
DI n.
5. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.
6. Each WRITE command may be to any bank.
PDF: 09005aef8565148a
1GbDDR2.pdf – Rev. AA 07/14 EN
106
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