MT47H128M8SH-187EITM View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
MT47H128M8SH-187EITM Datasheet PDF : 133 Pages
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1Gb: x4, x8, x16 DDR2 SDRAM
WRITE
5. tQH is derived from tHP: tQH = tHP - tQHS.
6. The data valid window is derived for each DQS transition and is tQH - tDQSQ.
7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.
Figure 57: Data Output Timing – tAC and tDQSCK
T01
CK#
CK
LDQS#/LDQS/DUQDSQ##/D/UQDSQoSr3
DQ (last data valid)
DQ (first data valid)
All DQs collectively4
T1
T2
T3
T3n T4
T4n T5
T5n T6
T6n
T7
tLZ (MIN)
tRPRE
tDQSCK2 (MIN)
tDQSCK2 (MAX) tHZ (MAX)
tRPST
T3
T3n
T4
T4n T5
T5n
T6
T6n
T3
T3n
T4
T4n T5
T5n
T6 T6n
T3
T3n
T4
T4n T5
T5n
T6
T6n
tLZ (MIN)
tAC5 (MIN)
tAC5 (MAX)
tHZ (MAX)
Notes:
1. READ command with CL = 3, AL = 0 issued at T0.
2. tDQSCK is the DQS output window relative to CK and is the long-term component of
DQS skew.
3. DQ transitioning after DQS transitions define tDQSQ window.
4. All DQ must transition by tDQSQ after DQS transitions, regardless of tAC.
5. tAC is the DQ output window relative to CK and is the “long term” component of DQ
skew.
6. tLZ (MIN) and tAC (MIN) are the first valid signal transitions.
7. tHZ (MAX) and tAC (MAX) are the latest valid signal transitions.
8. I/O balls, when entering or exiting High-Z, are not referenced to a specific voltage level,
but to when the device begins to drive or no longer drives, respectively.
WRITE
WRITE bursts are initiated with a WRITE command. DDR2 SDRAM uses WL equal to RL
minus one clock cycle (WL = RL - 1CK) (see READ (page 75)). The starting column and
bank addresses are provided with the WRITE command, and auto precharge is either
enabled or disabled for that access. If auto precharge is enabled, the row being accessed
is precharged at the completion of the burst.
Note: For the WRITE commands used in the following illustrations, auto precharge is
disabled.
During WRITE bursts, the first valid data-in element will be registered on the first rising
edge of DQS following the WRITE command, and subsequent data elements will be reg-
istered on successive edges of DQS. The LOW state on DQS between the WRITE com-
mand and the first rising edge is known as the write preamble; the LOW state on DQS
following the last data-in element is known as the write postamble.
The time between the WRITE command and the first rising DQS edge is WL ± tDQSS.
Subsequent DQS positive rising edges are timed, relative to the associated clock edge, as
±tDQSS. tDQSS is specified with a relatively wide range (25% of one clock cycle). All of
PDF: 09005aef8565148a
1GbDDR2.pdf – Rev. AA 07/14 EN
103
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