MT46V128M4TG-8 View Datasheet(PDF) - Micron Technology

Part Name

Description

MFG CO.

MT46V128M4TG-8

512Mb: x4, x8, x16 DDR SDRAM

Micron Technology 

READs

READ bursts are initiated with a READ command,

as shown in Figure 6.

The starting column and bank addresses are pro-

vided with the READ command and auto precharge is

either enabled or disabled for that burst access. If auto

precharge is enabled, the row being accessed is

precharged at the completion of the burst. For the ge-

neric READ commands used in the following illustra-

tions, auto precharge is disabled.

During READ bursts, the valid data-out element

from the starting column address will be available fol-

lowing the CAS latency after the READ command. Each

subsequent data-out element will be valid nominally

at the next positive or negative clock edge (i.e., at the

next crossing of CK and CK#). Figure 7 shows general

timing for each possible CAS latency setting. DQS is

driven by the DDR SDRAM along with output data.

The initial LOW state on DQS is known as the read

preamble; the LOW state coincident with the last data-

out element is known as the read postamble.

Upon completion of a burst, assuming no other com-

mands have been initiated, the DQs will go

High-Z. A detailed explanation of tDQSQ (valid data-

out skew), tQH (data-out window hold), the valid data

window are depicted in Figure 27. A detailed explana-

tion of tDQSCK (DQS transition skew to CK) and tAC

(data-out transition skew to CK) is depicted in Figure

28.

Data from any READ burst may be concatenated

with or truncated with data from a subsequent READ

command. In either case, a continuous flow of data can

be maintained. The first data element from the new

burst follows either the last element of a completed

burst or the last desired data element of a longer burst

which is being truncated. The new READ command

should be issued x cycles after the first READ com-

mand, where x equals the number of desired data ele-

ment pairs (pairs are required by the 2n-prefetch ar-

chitecture). This is shown in Figure 8. A READ com-

mand can be initiated on any clock cycle following a

previous READ command. Nonconsecutive read data

is shown for illustration in Figure 9. Full-speed random

read accesses within a page (or pages) can be performed

as shown in Figure 10.

ADVANCE

512Mb: x4, x8, x16

DDR SDRAM

CK#

CK

CKE HIGH

CS#

RAS#

CAS#

WE#

x4: A0-A9, A11, A12

x8: A0-A9, A11

x16: A0-A9

x8: A12

x16: A11, A12

A10

CA

EN AP

DIS AP

BA0,1

BA

CA = Column Address

BA = Bank Address

EN AP = Enable Auto Precharge

DIS AP = Disable Auto Precharge

DON’T CARE

Figure 6

READ Command

512Mb: x4, x8, x16 DDR SDRAM

512Mx4x8x16DDR_B.p65 – Rev. B; Pub 4/01

17

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001, Micron Technology, Inc.

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