MAX5100 View Datasheet(PDF) - Maxim Integrated

Part Name

Description

MFG CO.

MAX5100

+2.7V to +5.5V, Low-Power, Quad, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs

Maxim Integrated 

+2.7V to +5.5V, Low-Power, Quad, Parallel

8-Bit DAC with Rail-to-Rail Voltage Outputs

INPUT

LATCH A

DAC A

LATCH

DAC A

OUTA

D0–D7

INPUT

LATCH B

INPUT

LATCH C

DAC B

LATCH

DAC C

LATCH

DAC B

DAC C

OUTB

OUTC

AO

A1

Figure 2. Functional Diagram

INPUT

LATCH D

CONTROL

LOGIC

WR

DAC D

LATCH

LDAC

DAC D

REF SHDN

MAX5100

OUTD

Table 1. MAX5100 Address Table (Partial)

LDAC WR A1 A0

LATCH STATE

H

H X X Input and DAC data latched

H

L L L DAC A input latch transparent

L

H

X

X

All 4 DACs’ DAC latches

transparent

DAC A input registers transpar-

L

L L L ent and all 4 DACs’ DAC

latches transparent

H

L L H DAC B input latch transparent

H

L H L DAC C input latch transparent

H

L H H DAC D input latch transparent

H = High state, L = Low state, X = Don’t care

When WR is low, the addressed DAC’s input latch is

transparent. Data is latched when WR is high.

The MAX5100 LDAC feature allows simultaneous

updating of all four DACs. LDAC low latches the data in

the data registers to the DAC registers. If simultaneous

updating is not required, tie LDAC low to keep the DAC

latches transparent. If WR and LDAC are low simultane-

ously, avoid output glitches by ensuring that data is

valid before the two signals go low. When the device

powers up (i.e., VDD ramps up), all latches are internal-

ly preset with code 00 hex.

Applications Information

External Reference

The reference source resistance must be considerably

less than the reference input resistance. To keep within

1LSB error in an 8-bit system, RS must be less than

RREF / 256. Hence, maintain a value of RS <1kΩ to

ensure 8-bit accuracy. If VREF is DC only, bypass REF

to GND with a 0.1µF capacitor. Values greater than this

improve noise rejection.

Power Sequencing

The voltage applied to REF should not exceed VDD at

any time. If proper power sequencing is not possible,

connect an external Schottky diode between REF and

VDD to ensure compliance with the absolute maximum

ratings.

Power-Supply Bypassing and

Ground Management

Digital or AC transient signals on GND can create noise

at the analog output. Return GND to the highest-quality

ground available. Bypass VDD with a 0.1µF capacitor,

located as close to VDD and GND as possible.

Careful PC board ground layout minimizes crosstalk

between the DAC outputs and digital inputs.

Chip Information

TRANSISTOR COUNT: 6848

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