MAX11606 View Datasheet(PDF) - Maxim Integrated
Part Name
Description
MFG CO.
MAX11606 Datasheet PDF : 22 Pages
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MAX11606–MAX11611
Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packages
Configuration/Setup Bytes (Write Cycle)
A write cycle begins with the bus master issuing a
START condition followed by seven address bits (Figure
7) and a write bit (R/W = 0). If the address byte is suc-
cessfully received, the MAX11606–MAX11611 (slave)
issues an acknowledge. The master then writes to the
slave. The slave recognizes the received byte as the
setup byte (Table 1) if the most significant bit (MSB) is
1. If the MSB is 0, the slave recognizes that byte as the
configuration byte (Table 2). The master can write either
one or two bytes to the slave in any order (setup byte
then configuration byte; configuration byte then setup
byte; setup byte or configuration byte only; Figure 9). If
the slave receives a byte successfully, it issues an
acknowledge. The master ends the write cycle by issu-
ing a STOP condition or a repeated START condition.
When operating in HS mode, a STOP condition returns
the bus into F/S mode (see the HS Mode section).
MASTER TO SLAVE
SLAVE TO MASTER
A. ONE-BYTE WRITE CYCLE
1
7
11
8
11
S
SLAVE ADDRESS
WA
SETUP OR
CONFIGURATION BYTE
A
P or Sr
NUMBER OF BITS
MSB DETERMINES WHETHER
SETUP OR CONFIGURATION BYTE
B. TWO-BYTE WRITE CYCLE
1
7
11
8
1
8
11
S
SLAVE ADDRESS
WA
SETUP OR
CONFIGURATION BYTE
A
SETUP OR
CONFIGURATION BYTE
A P or Sr
Figure 9. Write Cycle
MSB DETERMINES WHETHER
SETUP OR CONFIGURATION BYTE
NUMBER OF BITS
Table 1. Setup Byte Format
BIT 7
(MSB)
REG
BIT 6
SEL2
BIT 5
SEL1
BIT 4
SEL0
BIT 3
CLK
BIT 2
BIP/UNI
BIT 1
RST
BIT 0
(LSB)
X
BIT
7
6
5
4
3
2
1
0
Maxim Integrated
NAME
REG
SEL2
SEL1
SEL0
CLK
BIP/UNI
RST
X
DESCRIPTION
Register bit. 1 = setup byte, 0 = configuration byte (see Table 2).
Three bits select the reference voltage and the state of AIN_/REF
(MAX11606/MAX11607/MAX11610/MAX11611) or REF (MAX11608/MAX11609) (Table 6).
Defaulted to 000 at power-up.
1 = external clock, 0 = internal clock. Defaulted to 0 at power-up.
1 = bipolar, 0 = unipolar. Defaulted to 0 at power-up (see the Unipolar/Bipolar section).
1 = no action, 0 = resets the configuration register to default. Setup register remains unchanged.
Don’t-care bit. This bit can be set to 1 or 0.
13
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