MAX1086EKA-T View Datasheet(PDF) - Maxim Integrated

Part Name

Description

MFG CO.

MAX1086EKA-T

150ksps, 10-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23

Maxim Integrated 

150ksps, 10-Bit, 2-Channel Single-Ended, and

1-Channel True-Differential ADCs in SOT23

TIMING CHARACTERISTICS (Figures 1 and 2)

(VDD = +2.7V to +3.6V, VREF = +2.5V for MAX1087/MAX1089, or VDD = +4.75V to +5.25V, VREF = +4.096V for MAX1086/MAX1088,

0.1µF capacitor at REF, fSCLK = 8MHz (50% duty cycle); AIN- = GND for MAX1088/MAX1089. TA = TMIN to TMAX, unless otherwise

noted. Typical values at TA = +25°C.)

PARAMETERS

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

SCLK Pulse Width High

SCLK Pulse Width Low

SCLK Fall to DOUT Transition

SCLK Rise to DOUT Disable

CNVST Rise to DOUT Enable

CNVST Fall to MSB Valid

CNVST Pulse Width

tCH

tCL

tDOT

tDOD

tDOE

tDOV

tCSW

CLOAD = 30pF

CLOAD = 30pF

CLOAD = 30pF

CLOAD = 30pF

38

ns

38

ns

60

ns

100

500

ns

80

ns

3.7

µs

30

ns

Note 1: Unipolar input.

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have

been removed.

Note 3: Offset nulled.

Note 4: The absolute input range for the analog inputs is from GND to VDD.

CNVST

•••

SCLK

•••

tDOE

HIGH-Z

DOUT

•••

Figure 1. Detailed Serial-Interface Timing Sequence

tCH

tCL

tDOT

tCSW

tDOD

HIGH-Z

DOUT

6kΩ

CL

GND

a) HIGH -Z TO VOH, VOL TO VOH, AND VOH TO HIGH -Z

DOUT

VDD

6kΩ

CL

GND

a) HIGH -Z TO VOL, VOH TO VOL, AND VOL TO HIGH -Z

Figure 2. Load Circuits for Enable/Disable Times

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