MAS3549F View Datasheet(PDF) - Micronas

Part Name

Description

MFG CO.

MAS3549F

MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec

Micronas 

DATA SHEET

MAS 35x9F

2.11.4.Control of the Signal Processing

Before starting the DSP, the controller should check

for a sufficient voltage supply (respective flag PUPn at

I2C

the

subaddress

appropriate

76hex). The DSP

bit in the Control

is enabled by

register (I2C

setting

subad-

dress 6Ahex). The nominal frequency of the crystal

oscillator must be written into D0:348. After an initial-

ization phase of 5 ms, the DSP data registers can be

accessed via I2C.

Input and output control is performed via memory loca-

tion D0:346 and D0:347. The serial input interface

SDIB is the default. The decoded audio can be routed

to either the S/PDIF, the SDO and the analog outputs.

The output clock signal at pin CLKO is defined in

D0:349.

All changes in the D0 memory cells become effective

synchronously upon setting the LSB of Main I/O Con-

trol (see Table 3–8 on page 32). Therefore, this cell

should always be written last.

The digital volume control (see Table 3–8 on page 32)

is applied to the output signal of the DSP. The

decoded audio data will be available at the SPDO out-

put interface in the next version.

The DSP does not have to be started if its functions

are not required, e.g., for routing audio through the

codec part of the IC via the A/D and the D/A convert-

ers.

2.11.5.Start-up of the Audio Codec

Before enabling the audio codec, the controller should

check for a sufficient voltage supply (respective flag

PUPn at I2C subaddress 76hex).

The audio codec is enabled by setting the appropriate

bit at the Control register (I2C subaddress 6Ahex). After

an initialization phase of 5 ms, the DSP data registers

can be accessed via I2C. The A/D and the D/A con-

verters must be switched on explicitly (register

00 00hex at I2C subaddress 6Chex). The D/A convert-

ers may either accept data from the A/D converters or

the output of the DSP, or a mix of both1) (register

00 06hex and 00 07hex at I2C subaddress 6Chex).

Finally, an appropriate output volume (register

00 10hex at I2C subaddress 6Chex) must be selected.

2.11.6.Power-Down

All analog outputs should be muted and the A/D and

the D/A converters must be switched off (register

00 10hex and 00 00hex at I2C subaddress 6Chex). The

DSP and the audio codec must be disabled (clear

DSP_EN and CODEC_EN bits in the Control register,

eI2nCablseubflaadgdsreinssthe6ACheoxn).troBl yregcilsetaerrin(gI2CbostuhbaDddCr/eDsCs

6Ahex), the microcontroller can power down the com-

plete system.

Micronas

1) mixer available in version A2 and later; in version

A1, please use selector 00 0Fhex.

June 30, 2004; 6251-505-1DS

21

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