M27V101-90F1TR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
M27V101-90F1TR Datasheet PDF : 15 Pages
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M27V101
Table 7. Read Mode DC Characteristics (1)
(TA = 0 to 70°C or –40 to 85°C; VCC = 3.3V ± 10%; VPP = VCC)
Symbol
Parameter
Test Condition
Min
Max
ILI
Input Leakage Current
0V ≤ VIN ≤ VCC
±10
ILO Output Leakage Current
0V ≤ VOUT ≤ VCC
±10
ICC Supply Current
E = VIL, G = VIL, IOUT = 0mA,
15
f = 5MHz, VCC ≤ 3.6V
ICC1 Supply Current (Standby) TTL
E = VIH
1
ICC2 Supply Current (Standby) CMOS
E > VCC – 0.2V, VCC ≤ 3.6V
20
IPP Program Current
VPP = VCC
10
VIL
Input Low Voltage
–0.3
0.8
VIH (2) Input High Voltage
2
VCC + 1
VOL Output Low Voltage
IOL = 2.1mA
0.4
Output High Voltage TTL
VOH
Output High Voltage CMOS
IOH = –400µA
IOH = –100µA
2.4
Vcc – 0.7V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Maximum DC voltage on Output is VCC +0.5V.
Unit
µA
µA
mA
mA
µA
µA
V
V
V
V
V
Table 8A. Read Mode AC Characteristics (1)
(TA = 0 to 70 °C or –40 to 85°; VCC = 3.3V ± 10%; VPP = VCC)
M27V101
Symbol Alt
Parameter
Test Condition
- 90 (3)
-100
Min Max Min Max
tAVQV tACC Address Valid to Output Valid
E = VIL, G = VIL
90
100
tELQV
tCE Chip Enable Low to Output Valid
G = VIL
90
100
tGLQV
tOE Output Enable Low to Output Valid
E = VIL
45
50
tEHQZ (2) tDF Chip Enable High to Output Hi-Z
G = VIL
0
30
0
30
tGHQZ (2) tDF Output Enable High to Output Hi-Z
E = VIL
0
30
0
30
tAXQX
tOH
Address Transition to Output
Transition
E = VIL, G = VIL 0
0
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurament conditions.
Unit
ns
ns
ns
ns
ns
ns
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling ca-
pacitors. It is recommended that a 0.1µF ceramic
capacitor be used on every device between VCC
and VSS. This should be a high frequency capaci-
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7µF bulk electrolytic capacitor should be
used between VCC and VSS for every eight devic-
es. The bulk capacitor should be located near the
power supply connection point. The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
5/15
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