ICS8344AYI-01 View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

MFG CO.

ICS8344AYI-01

LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER

Integrated Device Technology 

ICS8344I-01

LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER

APPLICATION INFORMATION

PRELIMINARY

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

Figure 1 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position the V_REF in

single ended levels. The reference voltage V_REF = V /2 is

DD

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V

DD

and R2/R1 = 0.609.

VDD

Single Ended Clock Input

V_REF

C1

0.1u

R1

1K

CLKx

nCLKx

R2

1K

FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

INPUTS:

CLK/nCLK INPUT:

For applications not requiring the use of the differential input,

both CLK and nCLK can be left floating. Though not required, but

for additional protection, a 1kΩ resistor can be tied from CLK to

ground.

OUTPUTS:

LVCMOS OUTPUT:

All unused LVCMOS output can be left floating. There should be

no trace attached.

LVCMOS CONTROL PINS:

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1kΩ resistor can be used.

IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER

8

ICS8344AYI-01 REV. B MAY 10, 2007

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