GS816218(B/D)/GS816236(B/D)/GS816272(C)
18Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
816218_r2_12;
816218_r2_13
816218_r2_13;
816218_r2_14
816218_r2_14;
816218_r2_15
816218_r2_15;
816218_r2_16
816218_r2_16;
816218_r2_17
Types of Changes
Format or Content
Content
Content
Content
Content
Format/Content
Page;Revisions;Reason
• Updated table on page 1
• Added 119-Bump BGA Pin Description table
• Created recommended operating conditions tables on pages
16 and 17
• Updated AC Electrical Characteristics table
• Added Sleep mode description on page 29
• Updated Ordering Information for 225 MHz part (changed
from 7ns to 6.5 ns)
• Updated BSR table (2 and 3 changed to X (value undefined))
• Added 250 MHz speed bin
• Deleted 180 MHz speed bin
• Updated AC Characteristics table
• Updated package designator for 209 BGA from B to C
• Updated VIH from 1.7 to 2.0
• Updated FT power numbers
• Updated Mb references from 16Mb to 18Mb
• Removed ByteSafe references
• Changed DP and QE pins to NC
• Updated ZZ recovery time diagram
• Add 165-bump FPBGA package
• Updated AC Test Conditions table and removed Output Load
2 diagram
• Removed parity I/O bit designation from 165 BGA pinout
• Removed Preliminary banner
• Removed BSR table
• Removed pin locations from pin description tables
• Removed 250 MHz and 225 MHz specs from x72
• Updated AC Characteristics table (tHZ, tOE, tOHZ equal to
tKQ (PL) for 250 MHz and 225 MHz)
• New timing diagrams added
• Updated format
• Updated timing diagrams
Rev: 2.17 11/2004
41/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology