CY2291I View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

MFG CO.

CY2291I

Three-PLL General Purpose EPROM Programmable Clock Generator

Cypress Semiconductor 

Pin Configurations

CY2291

20-pin SOIC

32XOUT 1

32K 2

CLKC 3

VDD 4

GND 5

XTALIN 6

XTALOUT 7

XBUF 8

CLKD 9

CPUCLK 10

20 32XIN

19 VBATT

18 SHUTDOWN/OE

17 S2/SUSPEND

16 VDD

15 S1

14 S0

13 CLKF

12 CLKA

11 CLKB

CY2291

Pin Summary

Name

Pin Number Description

32XOUT

1

32.768 kHz crystal feedback.

32K

2

32.768 kHz output (always active if VBATT is present).

CLKC

3

Configurable clock output C.

VDD

GND

XTALIN[1]

XTALOUT[1, 2]

4, 16

5

6

7

Voltage supply.

Ground.

Reference crystal input or external reference clock input.

Reference crystal feedback.

XBUF

8

Buffered reference clock output.

CLKD

9

Configurable clock output D.

CPUCLK

10

CPU frequency clock output.

CLKB

11

Configurable clock output B.

CLKA

12

Configurable clock output A.

CLKF

13

Configurable clock output F.

S0

14

CPU clock select input, bit 0.

S1

15

S2/SUSPEND

17

SHUTDOWN/OE 18

CPU clock select input, bit 1.

CPU clock select input, bit 2. Optionally enables suspend feature when LOW.[3]

Places outputs in three-state[4] condition and shuts down chip when LOW. Optionally, only

places outputs in three-state[4] condition and does not shut down chip when LOW.

VBATT

32XIN

19

Battery supply for 32.768-kHz circuit.

20

32.768-kHz crystal input.

Notes:

1. For best accuracy, use a parallel-resonant crystal, CLOAD ≈ 17 pF or 18 pF.

2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to crystal).

3. Please refer to application note “Understanding the CY2291, CY2292 and CY2295” for more information.

4. The CY2291 has weak pull-downs on all outputs (except 32K). Hence, when a three-state condition is forced on the outputs, the output pins are pulled LOW.

Document #: 38-07189 Rev. *A

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