CY2291I View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
MFG CO.
CY2291I Datasheet PDF : 14 Pages
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CY2291
Switching Characteristics, Industrial 3.3V
Parameter
t1
t3
t4
t5
t6
t7
t8
t9A
t9B
t9C
t9D
t10A
t10B
Name
Output Period
Output Duty
Cycle[11]
Rise Time
Fall Time
Output Disable
Time
Output Enable
Time
Skew
CPUCLK Slew
Clock Jitter[14]
Clock Jitter[14]
Clock Jitter[14]
Clock Jitter[14]
Lock Time for
CPLL
Lock Time for
UPLL and SPLL
Slew Limits
Description
Min.
Typ.
Max.
Unit
Clock output range, 3.3V CY2291I
operation
15
(66.6 MHz)
13000
ns
(76.923 kHz)
CY2291FI
Duty cycle for outputs, defined as t2 ÷ t1[12]
fOUT > 66 MHZ
Duty cycle for outputs, defined as t2 ÷ t1[12]
fOUT < 66 MHZ
Output clock rise time[13]
Output clock fall time[13]
16.66
(60 MHz)
13000
ns
(76.923 kHz)
40%
50%
60%
45%
50%
55%
3
5
ns
2.5
4
ns
Time for output to enter three-state mode after
SHUTDOWN/OE goes LOW
10
15
ns
Time for output to leave three-state mode after
SHUTDOWN/OE goes HIGH
10
15
ns
Skew delay between any identical or related out-
puts[3, 12, 15]
< 0.25
0.5
ns
Frequency transition rate
1.0
20.0
MHz/
ms
Peak-to-peak period jitter (t9A Max. – t9A min.),%
of clock period (fOUT < 4 MHz)
Peak-to-peak period jitter (t9B Max. – t9B min.)
(4 MHz < fOUT < 16 MHz)
Peak-to-peak period jitter
(16 MHz < fOUT < 50 MHz)
Peak-to-peak period jitter
(fOUT > 50 MHz)
Lock Time from Power-Up
<0.5
1
%
<0.7
1
ns
<400
500
ps
<250
350
ps
<25
50
ms
Lock Time from Power-Up
<0.25
1
ms
CPU PLL Slew Limits CY2291I
8
CY2291FI
8
66.6
MHz
60
MHz
Switching Waveforms
All Outputs, Duty Cycle and Rise/Fall Time
t1
t2
OUTPUT
t3
t4
Document #: 38-07189 Rev. *A
Page 10 of 14
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