ACS8510 View Datasheet(PDF) - Semtech Corporation

Part Name

Description

MFG CO.

ACS8510

Synchronous Equipment Timing Source for SONET or SDH Network Elements

Semtech Corporation 

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS

FINAL

Output Wander and Jitter

Wander and jitter present on the output clocks

are dependent on:

1. The magnitude of wander and jitter on the selected

input reference clock (in Locked mode)

2. The internal wander and jitter transfer characteristic

(in Locked mode)

3. The jitter on the local oscillator clock

4. The wander on the local oscillator clock (in Holdover

mode)

Wander and jitter are treated in different ways

to reflect their differing impacts on network

design. Jitter is always strongly attenuated,

whilst wander attenuation can be varied to suit

the application and operating state. Wander and

jitter attenuation is performed using a digital

phase locked loop (DPLL) with a programmable

bandwidth. This gives a transfer characteristic

of a low pass filter, with a programmable pole.

It is sometimes necessary to change the filter

dynamics to suit particular circumstances - one

example being when locking to a new source,

Table 8. Output Reference Source Selection Table

Port

Name

T01

T02

T03

T04

T05

T06

T07

T

08

T09

T010

T011

Output Port

Tech n ol og y

Frequencies Suppor ted

TTL/CMOS

1.544 MHz/2.048 MHz, 3.088 MHz/4.096 MHz, 6.176 MHz/8.192 MHz,

6.48 MHz (default), 12.352 MHz/16.384 MHz, 19.44 MHz, 25.92 MHz

TTL/CMOS

1.544 MHz/2.048 MHz, 3.088 MHz/4.096 MHz, 6.176 MHz/8.192 MHz,

12.352 MHz/16.384 MHz, 25.92 MHz, 38.88 MHz (default), 51.84 MHz

TTL/CMOS 19.44 MHz - fixed

TTL/CMOS 38.88 MHz - fixed

TTL/CMOS 77.76 MHz - fixed

LVDS/PECL

(LVDS default)

1.544 MHz/2.048 MHz, 3.088 MHz/4.096 MHz, 6.176 MHz/8.192 MHz,

12.352 MHz/16.384 MHz, 19.44 MHz, 38.88 MHz (default), 155.52 MHz,

311.04 MHz

PECL/LVDS

(PECL default)

19.44 MHz (default), 51.84 MHz, 77.76 MHz, 155.52 MHz

AMI

64/8 kHz (composite clock, 64 kHz + 8 kHz)

TTL/CMOS 1.544 MHz/2.048 MHz

TTL/CMOS FrSync, 8 kHz - with a 50:50 MSR

TTL/CMOS MFrSync, 2 kHz - with a 50:50 MSR

Note for Table 8.

Where 1.544 MHz/2.048 MHz is shown, 1.544 MHz is SONET, and 2.048 MHz is SDH. Pin SONSDHB controls the default

frequency output. Where the SONSDHB pin is High SONET is default, and when SONSDHB pin is Low SDH is default.

Revision 2.00/September 2003 Semtech Corp.

17

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