MAX97220A View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
MAX97220A Datasheet PDF : 19 Pages
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Differential Input DirectDrive
Line Drivers/Headphone Amplifiers
Applications Information
MAX9722 Compatibility
The MAX97220_ is compatible with the footprint of the
MAX9722. BIAS on the MAX97220_ is in the same posi-
tion as SVSS. On the MAX9722, SVSS is connected to
PVSS. For the MAX97220_, there is only one charge-
pump output that doubles as the amplifier’s negative
power-supply input. The connection of negative charge-
pump output and amplifier negative power-supply input
is internal on the MAX97220_ and external on the
MAX9722.
To implement a PCB that is compatible with both the MAX9722
and MAX97220_, put a capacitor pad from BIAS/SVSS
(MAX97220_/MAX9722 pin 11) to PGND. Also, place a 0I
resistor pad from BIAS/SVSS (MAX97220_/MAX9722 pin
11) to PVSS (pin 5 on both parts). Install the 0I resistor
when the MAX9722 is used and leave the resistor out of
circuit when the MAX97220_ is used (Figure 4).
Power Dissipation
While driving a headphone load, the IC dissipates a sig-
nificant amount of power. The maximum power dissipa-
tion is given in the Continuous Power Dissipation of the
Absolute Maximum Ratings section or can be calculated
by the following equation:
PD(MAX)
=
TJ(MAX)
qJA
−
TA
where TJ(MAX) is +150NC, TA is the ambient temperature,
and BJA is the reciprocal of the derating factor in NC/W
as specified in the Absolute Maximum Ratings section.
Since the IC is a stereo amplifier, the total maximum
internal power dissipation for a given VDD and load is
given by the following equation:
PD(MAX)
=
4VDD2
π2RL
If the internal power dissipation for a given application
exceeds the maximum allowed for a given package,
reduce power dissipation by decreasing supply voltage,
ambient temperature, input signal, or gain, or by increasing
load impedance.
The TQFN package features an exposed thermal pad
on its underside. This pad lowers the package's thermal
impedance by providing a direct heat conduction path
from the die to the PCB. Connect the exposed thermal
pad to PGND or an isolated plane.
2.5V TO 5.5V
1µF
10kI
0.47µF 10kI
0.47µF 10kI
10kI
10kI
0.47µF 10kI
0.47µF 10kI
PVDD SVDD
-INL
OUTL
+INL
BIAS
C1P
C1
CHARGE
1µF
MAX97220A PUMP
C1N
PVSS
+INR
OUTR
-INR
SHDN SGND PGND
10kI
1µF
0.1µF
OPEN
C2
1µF
2.5V TO 5.5V
1µF
10kI
1µF
0.47µF 10kI
-INL
+INL
PVDD SVDD
OUTL
1µF
SVSS
0.47µF 10kI
C1P
10kI
C1
CHARGE
1µF
0I
MAX9722 PUMP
C1N
0.47µF
10kI
10kI
+INR
PVSS
OUTR
1µF
-INR
0.47µF 10kI
SHDN SGND PGND
10kI
Figure 4. MAX97220A vs. MAX9722 PCB Layout
14
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