AD8310 View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
AD8310 Datasheet PDF : 24 Pages
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AD8310
COM
CP
INHI 8
CD
INLO 1
CM
2kΩ
4kΩ
COM
TOP-END
DETECTORS
TYP 2.2V FOR
3V SUPPLY,
3.2V AT 5V
S
125Ω
6kΩ
5 VPOS
6kΩ
Q1
~3kΩ
Q2
IE
S
2.4mA
2
COMM
Figure 24. Signal Input Interface
Occasionally, it might be desirable to use the dc-coupled
potential of the AD8310 in baseband applications. The main
challenge here is to present the signal at the elevated common-
mode input level, which might require the use of low noise, low
offset buffer amplifiers. In some cases, it might be possible to
use dual supplies of ±3 V, which allow the input pins to operate
at ground potential. The output, which is internally referenced
to the COMM pin (now at −3 V), can be positioned back to
ground level, with essentially no sensitivity to the particular
value of the negative supply.
OFFSET INTERFACE
The input-referred dc offsets in the signal path are nulled via
the interface associated with Pin 3, shown in Figure 25. Q1
and Q2 are the first-stage input transistors, having slightly
unbalanced load resistors, resulting in a deliberate offset voltage
of about 1.5 mV referred to the input pins. Q3 generates a small
current to null this error, dependent on the voltage at the
OFLT pin. When Q1 and Q2 are perfectly matched, this voltage
is about 1.75 V. In practice, it can range from approximately
1 V to 2.5 V for an input-referred offset of ±1.5 mV.
INPUT
125Ω
STAGE
MAIN GAIN
STAGES
Q1
16μA AT
Q2 BALANCE
S
gm
5 VPOS
TO LAST
DETECTOR
BIAS, 1.2V
Q3
36kΩ
OFLT
Q4
3
48kΩ
COFLT
AVERAGE
ERROR
CURRENT
33pF
2 COMM
Figure 25. Offset Interface and Offset-Nulling Path
In normal operation using an ac-coupled input signal, the
OFLT pin should be left unconnected. The gm cell, which is
gated off when the chip is disabled, converts a residual offset
(sensed at a point near the end of the cascade of amplifiers) to
a current. This is integrated by the on-chip capacitor, CHP, plus
any added external capacitance, COFLT, to generate the voltage
that is applied back to the input stage in the polarity needed to
null the output offset. From a small-signal perspective, this
feedback alters the response of the amplifier, which exhibits a
zero in its ac transfer function, resulting in a closed-loop, high-
pass −3 dB corner at about 2 MHz. An external capacitor lowers
the high-pass corner to arbitrarily low frequencies; using 1 μF,
the 3 dB corner is at 60 Hz.
OUTPUT INTERFACE
The nine detectors generate differential currents, having an
average value that is dependent on the signal input level, plus a
fluctuation at twice the input frequency. These are summed at
nodes LGP and LGN in Figure 26. Further currents are added at
these nodes to position the intercept by slightly raising the
output for zero input and to provide temperature compensation.
VPOS 5
LGP
FROM ALL
DETECTORS
LGN
0.4pF 1.25kΩ 1.25kΩ 0.4pF
1.25kΩ 1.25kΩ
BIAS
60μA
COMM 2
2μA/dB
R1
3kΩ
4kΩ 4kΩ
6 BFIN
Figure 26. Simplified Output Interface
0.2pF
BIAS
4
3kΩ VOUT
1kΩ
Rev. E | Page 12 of 24
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