Logic Symbols
74F160A
IEEE/IEC
74F162A
74F160A
Unit Loading/Fan Out
74F162A
Pin Names
Description
U.L.
Input IIH/IIL
HIGH/LOW Output IOH/IOL
CEP
Count Enable Parallel Input
1.0/1.0 20 µA/−0.6 mA
CET
Count Enable Trickle Input
1.0/2.0 20 µA/−1.2 mA
CP
Clock Pulse Input (Active Rising Edge)
1.0/1.0 20 µA/−0.6 mA
MR (74F160A) Asynchronous Master Reset Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA
SR (74F162A) Synchronous Reset Input (Active LOW)
1.0/2.0 20 µA/−1.2 mA
P0–P3
PE
Parallel Data Inputs
Parallel Enable Input (Active LOW)
1.0/1.0
1.0/2.0
20 µA/−0.6 mA
20 µA/−1.2 mA
Q0–Q3
TC
Flip-Flop Outputs
Terminal Count Output
50/33.3
50/33.3
−1 mA/20 mA
−1 mA/20 mA
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