VSC9112(2000) View Datasheet(PDF) - Vitesse Semiconductor
Part Name
Description
MFG CO.
VSC9112 Datasheet PDF : 2 Pages
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SONET/SDH IP/ATM Framer and Mapper
Product Brief
VSC9112
Framers
and
Mappers
Features Continued:
Line Interface
• 16-bit 155 MHz Line
Interface
• Synchronization for
STS-192 Applications
Special Features
• Extensive Packet / Cell
Performance Monitoring
Features
• 16 Kb Packet / Cell FIFO for
Full Packet Encapsulation
• Programmable Error Dis-
carding and Label Filtering
• Rx and Tx Timestamp
Feature for Performance
Monitoring Applications
Miscellaneous Features
• Generic 8-bit CPU Interface
• Compliant JTAG Boundary
Scan Interface
• Five Loopback Modes for
Test and Diagnostic
Applications
• 0.35 micron CMOS, 352-pin
SBGA, 3.0 Watts Maximum
VSC9112 Block Diagram
TLCLK+/-
TLSYNC+/-
TLCLKOUT+/-
TLOUT[15..0]+/-
TLPRTY+/-
TLFP+/-
CLKRSTEN
RLCLK+/-
RLIN[15..0]+/-
RLPRTY+/-
RLFP+/-
Transport Overhead Insertion
TOAP
32
Section
Generation
TSOP
32
Line
Generation
TLOP
32
SPE/Path
Generation
TPOP
32 Packet/ATM
Mapping
TPP/TACP
Section Trace
Buffer
SSTB
Path Trace
Buffer
SPTB
32
LIF
Section
32
Termination
RSOP
Line
32
Termination
RLOP
SPE/Path
Termination
RPOP
32 Packet/ATM
Demapping
RPP/RACP
Transport Overhead Extraction
ROAP
BERM
VSC9112 Reference Board
JTAG TAP
32
32
PIF/UIF
CPU
TFCLK
TFCLKO
TENB
DTPA
TSOP
TPRTY
TDAT[31:0]
TMOD[1..0]
TEOP
TERR
RFCLK
RFCLKO
RENB
RVAL
RSOP
RPRTY
RDAT[31:0]
RMOD[1..0]
REOP
RERR
GPIOO[7..0]
PMTICK
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