WED9LC6416V
FIG. 10 SDRAM PAGE WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 16 17 18 19
SDCLK
SDCE
SDRAS
SDCAS
ADDR
RAa
CAa RBb
CBb
CAc
CBd
Note 2
BA
SDA10
RAa
DQ
SDWE
BWE
Row Active
(A-Bank)
RBb
tCDL
tRDL
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 DBd1
Row Active
(B-Bank)
Write
(A-Bank)
Write
(B-Bank)
Note 1
Write
(A-Bank)
Write
Precharge
(B-Bank) (Both Banks)
DON’T CARE
NOTES:
1. To interrupt burst write by Row precharge, BWE should be asserted to mask invalid input data.
2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same.
January 20001
19
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