CD40102BMS View Datasheet(PDF) - Intersil

Part Name

Description

MFG CO.

CD40102BMS

CMOS 8-Stage Presettable Synchronous Down Counters

Intersil 

Logic Diagrams

CD40102BMS, CD40103BMS

LSD

J0

J1

J2

J3

*4

*5

*6

* 7 (MSB)

A

B

TO

FF1 - FF7

C

CLR

*2

SPE

* 15

APE

*9

CLOCK

*1

CLR

CLR

SPE

SPE

APE

CL

CL

J

FF3

Q

Q

CI

J

Q

FF1

CI

J

Q

FF2

CI

J

Q

FF3

CI Q

TO

FF1 - FF7

D

CI/CE

E

*3

J4

* 10

A

B

C

J5

* 11

J6

* 12

MSD

J7

* 13 (MSB)

14

CARRY OUT/

ZERO DETECT

J

FF4

Q

CI

J

Q

FF5

CI

J

Q

FF6

CI

J

FF7

Q

CI

VDD

D

VSS

*ALL INPUTS ARE

PROTECTED BY COS/MOS

E

PROTECTION NETWORK

FIGURE 1. LOGIC DIAGRAM FOR CD40102BMS

7-1300

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