MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad 2-Input Data
Selector/Multiplexer with
3-State Outputs
High–Performance Silicon–Gate CMOS
The MC74HC257 is identical in pinout to the LS257. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device selects a (4–bit) nibble from either the A or B inputs as
determined by the Select input. The nibble is presented at the outputs in
noninverted form when the Output Enable pin is at a low level. A high level on
the Output Enable pin switches the outputs into the high–impedance state.
The HC257 is similar in function to the HC157 which do not have 3–state
outputs.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 108 FETs or 27 Equivalent Gates
LOGIC DIAGRAM
NIBBLE
A INPUT
NIBBLE
B INPUT
A0 2
A1 5
A2 11
A3 14
B0 3
B1 6
B2 10
B3 13
4 Y0
7 Y1 NONINVERTING
9
Y2
NIBBLE
OUTPUT
12 Y3
SELECT 1
OUTPUT 15
ENABLE
PIN 16 = VCC
PIN 8 = GND
MC74HC257
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
D SUFFIX
SOIC PACKAGE
CASE 751B–05
ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXD
Plastic
SOIC
PIN ASSIGNMENT
SELECT 1
A0 2
B0 3
16 VCC
15
OUTPUT
ENABLE
14 A3
Y0 4
A1 5
13 B3
12 Y3
B1 6
Y1 7
11 A2
10 B2
GND 8
9 Y2
FUNCTION TABLE
Inputs
Output
Enable Select
Outputs
Y0 – Y3
H
X
Z
L
L
A0 – A3
L
H
B0 – B3
X = don’t care
Z = high impedance
A0 – A3, B0 – B3 = the levels of the
respective Nibble Inputs.
10/95
© Motorola, Inc. 1995
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