PEB22320 View Datasheet(PDF) - Infineon Technologies
Part Name
Description
MFG CO.
PEB22320 Datasheet PDF : 45 Pages
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PEB 22320
Functional Description
2.2.2 Output Jitter
In the absence of any input jitter the PRACT generates the output jitter, which is specified
in table 5.
Note: The generated output jitter on the line is the same as the output jitter of the system
clocks.
2.3 Local Loopback
The local loopback mode disconnects the receive lines RL1 and RL2 from the receiver.
Instead of the signals coming from the line the data provided at XTIP and XTIN are
routed through the receiver. The XDIN and XDIP signals continue to be transmitted on
the line. The local loopback occurs in response to LL going high.
2.4 Remote Loopback
In the remote loopback mode the clock and data recovered from the line inputs RL1 and
RL2 are routed back to the line outputs XL1 and XL2 via the transmitter. As in normal
mode they are also output at RDOP and RDON. XDIP and XDIN are disconnected from
the transmitter.
The remote loopback mode is selected by a high RL signal.
2.5 Bypass Jitter Attenuator
If the JATT pin is set to low the jitter attenuator (FIFO) is bypassed and the propagation
delay from the line to the dual rail interface is reduced by the path time of the FIFO. Also
in this mode the jitter in the system clocks (CLK2M, CLK4M, FSC) is attenuated.
2.6 Microprocessor Interface
The PRACT is fully controlled by six parallel data lines (LS0, LS1, LS2, LL, RL and JATT)
and one control line (CS). To adapt the device to a standard microprocessor interface
the low state of CS is decoded from the microprocessor address, CS, WR and ALE lines.
To hardwire the chip, CS must be fixed to ground.
2.7 Receiver Loss of Signal Indication
In the case that the signal at the line receiver input (pins RL1, RL2) becomes smaller
than Vin ≤ 0.3 VOP loss of signal is indicated. This voltage value corresponds to a line
attenuation of about 14 dB in the CEPT case. This is performed by turning both signals
RDOP, RDON after at least 32 bits simultaneously to 5 V, i.e. a logical 0 on both lines.
The following ACFA processes this indication for the system. In this mode the PRACT
synchronizes to the clock at the SYNC pin.
Semiconductor Group
22
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