MC14526BFL1 View Datasheet(PDF) - ON Semiconductor

Part Name

Description

MFG CO.

MC14526BFL1

Presettable 4-Bit Down Counters

ON Semiconductor 

MC14526B

Presettable 4-Bit Down

Counters

The MC14526B binary counter is constructed with MOS P–channel

and N–channel enhancement mode devices in a monolithic structure.

This device is presettable, cascadable, synchronous down counter

with a decoded “0” state output for divide–by–N applications. In

single stage applications the “0” output is applied to the Preset Enable

input. The Cascade Feedback input allows cascade divide–by–N

operation with no additional gates required. The Inhibit input allows

disabling of the pulse counting function. Inhibit may also be used as a

negative edge clock.

This complementary MOS counter can be used in frequency

synthesizers, phase–locked loops, and other frequency division

applications requiring low power dissipation and/or high noise

immunity.

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Logic Edge–Clocked Design — Incremented on Positive Transition

of Clock or Negative Transition of Inhibit

• Asynchronous Preset Enable

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)

Symbol

Parameter

Value

Unit

VDD

DC Supply Voltage Range

– 0.5 to +18.0

V

Vin, Vout Input or Output Voltage Range – 0.5 to VDD + 0.5

V

(DC or Transient)

Iin, Iout

Input or Output Current

(DC or Transient) per Pin

±10

mA

PD

Power Dissipation,

per Package (Note 3.)

500

mW

TA

Operating Temperature Range

– 55 to +125

°C

Tstg

Storage Temperature Range

– 65 to +150

°C

TL

Lead Temperature

(8–Second Soldering)

260

°C

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

v v high–impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS (Vin or Vout) VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,

either VSS or VDD). Unused outputs must be left open.

http://onsemi.com

PDIP–16

P SUFFIX

CASE 648

MARKING

DIAGRAMS

16

MC14526BCP

AWLYYWW

1

16

SOIC–16

DW SUFFIX

CASE 751G

14526B

AWLYYWW

SOEIAJ–16

F SUFFIX

CASE 966

1

16

MC14526B

AWLYWW

1

A

= Assembly Location

WL or L = Wafer Lot

YY or Y = Year

WW or W = Work Week

ORDERING INFORMATION

Device

Package

Shipping

MC14526BCP

MC14526BDW

PDIP–16

SOIC–16

2000/Box

47/Rail

MC14526BDWR2 SOIC–16 1000/Tape & Reel

MC14526BF

SOEIAJ–16 See Note 1.

1. For ordering information on the EIAJ version of

the SOIC packages, please contact your local

ON Semiconductor representative.

© Semiconductor Components Industries, LLC, 2000

1

March, 2000 – Rev. 3

Publication Order Number:

MC14526B/D

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