ST5088
Table 2: Control Register CR0 Functions
7 65 43 21 0
F1 F0 MA IA DN FF B7 DL
Function
00
01
10
11
MCLK = 512 kHz
MCLK = 1.536 MHz
MCLK = 2.048 MHz
MCLK = 2.560 MHz
00
01
10
11
MU-law; CCITT D3-D4
MU-law; Bare Coding
A-law including even bit inversion
A-law; Bare Coding
0
Delayed data timing
1
Non delayed data timing
0
B1 and B2 consecutive
1
B1 and B2 separated
0
8 bits time-slot
1
7 bits time-slot
0 Normal operation
1 Digital Loop-back
*:
state at power on initialization
(1):
significant in COMBO I/II mode only
(1)
*
(1)
*
*
(1)
(1)
*
(1)
(1)
*
*
Table 3: Control Register CR1 Functions
76543210
HFE ALE DO MR MX EN T1 T0
Function
0
HFO / HFI pins disabled
1
HFO / HFi pins enabled
0
Anti-larsen disabled
1
Anti-larsen enabled
0
L0 latch is put in high impedance
1
L0 latch set to 0
0
DR connected to rec. path
1
CR2 connected to rec. path
0
Trans path connected to DX
1
CR3 connected to DX
0
voice data transfer disable
1
voice data transfer enable
0 0 B1 channel selected
0 1 B2 channel selected
1 0 B1* channel selected
1 1 B2* channel selected
*:
(1):
(2):
14/33
state at power on initialization
significant in COMBO I / II mode only
significant in GCI mode only.
*
*
*
*
(1)
(1)
*
(1)
(1)
*
*
(2)
(2)