SMS8198 View Datasheet(PDF) - Summit Microelectronics
Part Name
Description
MFG CO.
SMS8198
Summit Microelectronics
SMS8198 Datasheet PDF : 14 Pages
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SMS8198
PIN CONFIGURATIONS
8-Pin SOIC
NC 1
TRI_RESET# 2
NC 3
GND 4
8 VCC
7 WP
6 SCL
5 SDA
TRI_RESET# - is an active low open drain output. It is
driven low whenever VCC is below VTRIP. TRI_RESET# is
also an input and can be used to debounce a switch input
or perform signal conditioning. The TRI_RESET# pin
does have an internal pull-up and should be left uncon-
nected if the signal is not used in the system. However,
when the pin is tied to a system TRI_RESET# line an
external pull-up resistor should be employed.
Write Protect (WP) - All write operations can be disabled
by maintaining WP > VIH.
2036 T PCon 2.0
No Connects (NC) - The no connect inputs are unused by
the SMS8198; however, to insure proper operation they
can be unconnected or tied to ground. They must not be
tied to VCC.
ENDURANCE AND DATA RETENTION
PIN NAMES
SDA
SCL
TRI_RESET#
GND
VCC
WP
NC
Serial Data I/O
Serial Clock Input
Reset Output
Ground
Supply Voltage
Write Protect
No Connect
The SMS8198 is designed for applications requiring up to
100,000 erase/write cycles and unlimited read cycles. It
provides 100 years of secure data retention, with or
without power applied, after the execution of 100,000
erase/write cycles.
RESET CONTROLLER DESCRIPTION
The device provides a precise reset output to a
microcontroller and it’s associated circuitry ensuring cor-
rect system operation during power-up/down conditions
and brownout situations. The output is open drain, allow-
ing control of the reset function by multiple devices.
PIN DESCRIPTIONS
Serial Clock (SCL) - The SCL input is used to clock data
into and out of the device. In the WRITE mode, data must
remain stable while SCL is HIGH. In the READ mode, data
is clocked out on the falling edge of SCL.
Serial Data (SDA) - The SDA pin is a bidirectional pin
used to transfer data into and out of the device. Data may
change only when SCL is LOW, except START and STOP
conditions. It is an open-drain output and may be wire-
ORed with any number of open-drain or open-collector
outputs.
During power-up the reset output remains in a fixed active
state until VCC passes through the reset threshold and
remains above the threshold for tPURST. The reset output
is valid whenever VCC is equal to or greater than 1V. If VCC
falls below the threshold for more than tGLITCH the device
will immediately generate a reset and drive the output.
The reset pin is an I/O; therefore, forcing the pin to the
active state can also manually reset the device. Because
the I/O needs to be an open drain, the internal timer can
only be triggered by the leading edge of the input. The
resulting reset output will either be tPURST, or the externally
applied reset signal, whichever is longer. This can provide
an affective debounce or reset signal extender solution.
2036 5.0 4/18/00
4
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