LC89973M View Datasheet(PDF) - SANYO -> Panasonic

Part Name

Description

MFG CO.

LC89973M

PAL CCD Delay Line

SANYO -> Panasonic 

Block Diagram

LC89973M

Control Pin Function

CONT

Low

High

Mode (representative example)

PAL/GBI

4.43 NTSC

Chrominance signal delay

(CCD bits)

2 H (1705) + 0 H (2.5)

1 H (853) + 0 H (2.5)

Luminance signal delay

(CCD bits)

1 H (848.5)

1 H (848.5)

Switching Voltage Levels

Low/high

Symbol

min

typ

max

Unit

Low

VL

–0.3

0.0

+0.5

V

High

VH

2.0

5.0

6.0

V

Note: Since the control pin has a built-in pull-down resistor, the pin will be set to the low state if left open.

FSC OUT Pin Function

This pin provides a buffer output for the clock signal input to the CLK pin.

Note: Since this pin has a built-in pull-up resistor, the pin voltage will go to the supply voltage and output will cease if left open.

No. 5114-7/8

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