
Truth Table
Clear
L
H
H
H
(Each Flip-Flop)
Inputs
Clock
D
X
X
↑
H
↑
L
L
X
Outputs
Q
L
H
L
Q0
H = HIGH Level (Steady State)
L = LOW Level (Steady State)
X = Don’t Care
↑ = Transition from LOW-to-HIGH level
Q0 = The level of Q before the indicated steady state input conditions were
established
Logic Diagram
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