Truth Table
Operating Mode
Inputs
MR CP
Dn
Reset (Clear)
Load “1”
Load “0”
L
X
X
H
h
H
l
H HIGH Voltage Level steady state
h HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition
L LOW Voltage Level steady state
I LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition
X Immaterial
LOW-to-HIGH clock transition
Logic Diagram
Output
Qn
L
H
L
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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