SAB9080 View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
SAB9080 Datasheet PDF : 24 Pages
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Philips Semiconductors
NTSC Picture-In-Picture (PIP) controller
Preliminary specification
SAB9080
PINNING
SYMBOL
Vref(B)(MA)
MU
VDDA(MF)
VSSA(MA)
VDDA(MA)
VDDA(DA)
VSSA(DA)
DY
Vbias(DA)
DV
Vref(T)(DA)
DU
Vref(B)(DA)
VDDD(DA)
VSSD(DA)
VSSD(P1)
VDDD(P1)
VSSD(T1)
VSSD(T2)
VDDD(RP)
n.c.
VSSD(T3)
n.c.
T5
T4
T3
T2
T1
T0
TC
VDDD(RL)
VSSD(RL)
VSSD(RM)
VDDD(RM)
TCLK
TM
TCBD
TCBC
TCBR
VSSD(T4) to VSSD(T7)
1999 Nov 12
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 to 29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48 to 51
TYPE
DESCRIPTION
I/O analog bottom reference voltage for main channel ADCs
I analog U input for main channel
S analog supply voltage for main channel front-end buffers
S analog ground for main channel ADCs
S analog supply voltage for main channel ADCs
S analog supply voltage for DACs
S analog ground for DACs
O analog Y output of DAC
I/O input/output analog bias reference voltage for DACs
O analog V output of DAC
I/O input/output analog top reference voltage for DACs
O analog U output of DAC
I/O analog bottom reference voltage for DACs
S digital supply voltage for DACs
S digital ground for DACs
S digital ground for periphery
S digital supply voltage for periphery
S digital ground for test
S digital ground for test
S digital supply voltage for memory periphery
− not connected
S digital ground for test
− not connected
I/O test data input/output bit 5 (CMOS levels)
I/O test data input/output bit 4 (CMOS levels)
I/O test data input/output bit 3 (CMOS levels)
I/O test data input/output bit 2 (CMOS levels)
I/O test data input/output bit 1 (CMOS levels)
I/O test data input/output bit 0 (CMOS levels)
I test control input (CMOS levels)
S digital supply voltage for memory logic
S digital ground for memory logic
S digital ground for memory core
S digital supply voltage for memory core
I test clock input (CMOS levels)
I test mode input (CMOS levels)
I test control block data input (CMOS levels)
I test control block clock input (CMOS levels)
I test control block reset input (CMOS levels)
S digital ground for test
4
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