SAB9080 View Datasheet(PDF) - Philips Electronics

Part Name

Description

MFG CO.

SAB9080

NTSC Picture-In-Picture (PIP) controller

Philips Electronics 

Philips Semiconductors

NTSC Picture-In-Picture (PIP) controller

Preliminary specification

SAB9080

SDSEL (REPLAY MODE)

Bits SDSel<5:0> select which PIP is read from memory.

Valid numbers are dependent on the maximum value of

SLSel.

SFBLKPKOFF

Bits SFBlkPkOff<1:> shift signals FBL and PKOFF with

respect to the YUV output, by half pixels, see Table 4.

Table 4 Shifts of FBL and PKOFF

SFBlkPkOff<1:0>

00

01

10

11

SHIFT OF FBL AND PKOFF

no shift

+0.5 pixel

−0.5 pixel

−1 pixel

I2CHOLD

Bit I2CHold controls the updating of the I2C-bus controlled

function towards the PIP. If set to logic 1, some updates

are on hold until the bit is set to logic 0. At the next main

Vsync, all settings are passed to the PIP functions.

The bits and bytes that are on hold when bit I2CHold is set

to logic 1 are:

• MPIPON, SPIPON, DNonint and PipMode

• SHBlow and SVBlow

• SHRed and SVRed

• BGHfp and BGVfp

• SDHfp and SDVfp

• SHPic and SVPic

• BGOn, BOn and Prio

• BSel, SBBrt and SBCol

• SDSel

• MDHfp and MDVfp

• HBWidth and VBWidth.

SV2

When set to logic 0, bit SV2 limits the range of the MAHfp

and SAHfp parameters. Otherwise (bit SV2 set to logic 1),

the parameters have their maximum range (which is

recommended).

HBWIDTH AND VBWIDTH

Bits HBWidth<2:0> and VBWidth<2:0>control the

horizontal and vertical border sizes in steps of two pixels

and one line. The default horizontal border size is four

pixels and the vertical border size is two lines per field.

Default means after power-up and no I2C-bus data sent to

the PIP controller.

NOTES

1. When the input signals for the main and/or subchannel

are non-interlaced, joint line errors can occur. When

non-interlaced signals are input, the SAB9080

switches automatically to the non-interlaced mode.

2. When the prevent joint line error algorithm is switched

off (AlgOff is set to logic 1), joint line errors can still

occur in the 2-Field mode.

Acquisition channel ADCs and clamping

The analog input signals are converted to digital signals by

three ADCs per channel. The resolution of the ADCs is

8 bits (DNL is 7 bits and INL is 6 bits) and the sampling is

performed at the system clock frequency of 28 MHz for the

Y input. A bias voltage (Vbias) is used to decouple the AC

components on internal references.

The inputs should be AC coupled and an internal clamp

circuit (using external clamp capacitors) will clamp the

input to a level derived internally from Vref(B)(MA/SA) for the

luminance channels and, for the chrominance channels, to

(Vref(T)(MA/SA) + Vref(B)(MA/SA))/2 + LSB/2. The clamping

starts at the active edge of the burst key. Internal video

buffers amplify the standard Y, U and V input signals to

the correct ADC levels.

SV1

Bit SV1 controls the internal horizontal offset of the

background. When set to logic 0, the offset is 0.86 µs;

when set to logic 1, the offset is 4.56 µs.

PLL

The PLL generates an internal system clock from the

fHSYNC of 1792 × fHSYNC, which is approximately 28 MHz.

DACs and video buffers

The 28 MHz digital video signals are fed to the 8-bit DACs

that produce the required analog video signals. The video

buffers amplify these signals prior to being fed to the

output to drive another device.

1999 Nov 12

11

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