datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

P/N + Description + Content Search

Search Word's :
Part Name(s) : MPS3500BL-100M
BOWEI Integrated Circuits CO.,LTD.
BOWEI Integrated Circuits CO.,LTD.
Description : Low phase noise fixed frequency synthesizer

Features
Low phase noise -110dBc/Hz@10kHz
● Small size 25*20*4.5mm
Low power supply +5V
frequency range 300~7500MHz
● Custom design available

Description : fixed frequency phase locked synthesizer

Features
● Small size 20*15*4mm
Low power supply +5V
frequency range 10~7500MHz
● Dual fixed frequency output available, TTL control

Description : fixed frequency synthesizer

Features
● Small size 12*12*4mm
Low power supply +5V
frequency range 300~5000MHz
● Dual fixed frequency output available, TTL control

Analog Devices
Analog Devices
Description : Low phase noise, Fast Settling PLL frequency synthesizer

GENERAL DESCRIPTION
The ADF4193 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture is specifically designed to meet the GSM/EDGE lock time requirements for base stations. It consists of a Low noise, digital phase frequency detector (PFD), and a precision differential charge pump. There is also a differential amplifier to convert the differential charge pump output to a single-ended voltage for the external voltage-controlled oscillator (VCO).

FEATURES
   New, fast settling, fractional-N PLL architecture
   Single PLL replaces ping-pong synthesizers
   frequency hop across GSM band in 5 µs with phase settled
      by 20 µs
   0.5° rms phase error at 2 GHz RF output
   Digitally programmable output phase
   RF input range up to 3.5 GHz
   3-wire serial interface
   On-chip, Low noise differential amplifier
   phase noise figure of merit: −216 dBc/Hz
   Loop filter design possible using ADIsimPLL™
   Qualified for automotive applications

APPLICATIONS
   GSM/EDGE base stations
   PHS base stations
   Instrumentation and test equipment

Description : Low phase noise, Fast Settling PLL frequency synthesizer (Rev - RevG)

GENERAL DESCRIPTION
The ADF4193 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture is specifically designed to meet the GSM/EDGE lock time requirements for base stations. It consists of a Low noise, digital phase frequency detector (PFD), and a precision differential charge pump. There is also a differential amplifier to convert the differential charge pump output to a single-ended voltage for the external voltage-controlled oscillator (VCO).

FEATURES
   New, fast settling, fractional-N PLL architecture
   Single PLL replaces ping-pong synthesizers
   frequency hop across GSM band in 5 µs with phase settled
      by 20 µs
   0.5° rms phase error at 2 GHz RF output
   Digitally programmable output phase
   RF input range up to 3.5 GHz
   3-wire serial interface
   On-chip, Low noise differential amplifier
   phase noise figure of merit: −216 dBc/Hz
   Loop filter design possible using ADIsimPLL™
   Qualified for automotive applications

APPLICATIONS
   GSM/EDGE base stations
   PHS base stations
   Instrumentation and test equipment

Description : Low phase noise, Fast Settling PLL frequency synthesizer

GENERAL DESCRIPTION
The ADF4193 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture is specifically designed to meet the GSM/EDGE lock time requirements for base stations. It consists of a Low noise, digital phase frequency detector (PFD), and a precision differential charge pump. There is also a differential amplifier to convert the differential charge pump output to a single-ended voltage for the external voltage-controlled oscillator (VCO).

FEATURES
   New, fast settling, fractional-N PLL architecture
   Single PLL replaces ping-pong synthesizers
   frequency hop across GSM band in 5 µs with phase settled
      by 20 µs
   0.5° rms phase error at 2 GHz RF output
   Digitally programmable output phase
   RF input range up to 3.5 GHz
   3-wire serial interface
   On-chip, Low noise differential amplifier
   phase noise figure of merit: −216 dBc/Hz
   Loop filter design possible using ADIsimPLL
   Qualified for automotive applications

APPLICATIONS
   GSM/EDGE base stations
   PHS base stations
   Instrumentation and test equipment

Description : Low phase noise, Fast Settling PLL frequency synthesizer (Rev - RevB)

GENERAL DESCRIPTION
The ADF4193 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture is specifically designed to meet the GSM/EDGE lock time requirements for base stations. It consists of a Low noise, digital phase frequency detector (PFD), and a precision differential charge pump. There is also a differential amplifier to convert the differential charge pump output to a single-ended voltage for the external voltage-controlled oscillator (VCO).

FEATURES
   New, fast settling, fractional-N PLL architecture
   Single PLL replaces ping-pong synthesizers
   frequency hop across GSM band in 5 μs with phase settled
      by 20 μs
   0.5° rms phase error at 2 GHz RF output
   Digitally programmable output phase
   RF input range up to 3.5 GHz
   3-wire serial interface
   On-chip, Low noise differential amplifier
   phase noise figure of merit: −216 dBc/Hz
   Loop filter design possible using ADI SimPLL

APPLICATIONS
   GSM/EDGE base stations
   PHS base stations
   Instrumentation and test equipment

Fujitsu
Fujitsu
Description : Dual Serial Input PLL frequency synthesizer

DESCRIPTION
The Fujitsu MB15F05L is a serial input phase Locked Loop (PLL) frequency synthesizer with a 1800MHz and a 233.15MHz prescalers. A 64/65 or a 128/129 for the 1800MHz prescaler, and a 16/17 for the 233.15MHz prescaler can be selected that enables pulse swalLow operation.

FEATURES
• High frequency operationRF synthesizer: 1800MHz max. / IF synthesizer: 233.15MHz fixed
Low power supply voltage: VCC = 2.7 to 3.6V
• Very Low power supply current : ICC = 5.0 mA typ. (Vcc = 3V)
• Power saving function : Supply current at power saving mode Typ.0.1µA (Vcc=3V), Max.10µA (IPS1=IPS2)
• Dual modulus prescaler : 1800MHz prescaler(64/65,128/129)
• Serial input 14–bit programmable reference divider: R = 5 to 16,383
• Serial input 18–bit programmable divider consisting of:
    - Binary 7–bit swalLow counter: 0 to 127
    - Binary 11–bit programmable counter: 5 to 2,047
• On–chip high performance charge pump circuit and phase comparator, achieving high–speed lock–up and Low phase noise
• On–chip phase control for phase comparator
• Wide operating temperature: Ta = -40 to 85˚C

Description : THRU-HOLE Tuning Fork

FEATURES

• Miniature Packages

Low Cost

• Cold Weld Design

• Long Term Stability

• Tight Tolerance


NIHON DEMPA KOGYO
NIHON DEMPA KOGYO
Description : Oven-Controlled Crystal Oscillator

Oven-Controlled Crystal Oscillator (OCXO) for fixed Communication Equipment

Features
● Compact.
● Excellent rise characteristics.
● Excellent phase noise characteristics.
● Excellent aging characteristics.

Main Application
● Mobile communication base station
● Measuring instrument
synthesizer
● Exchanger
● High-end router

12345678910 Next

All Rights Reserved© datasheetbank.com  [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]